公开(公告)号：US20120313178A1

公开(公告)日：2012-12-13

申请号：US13158479

申请日：2011-06-13

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/3205 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US08704294B2

公开(公告)日：2014-04-22

申请号：US13158479

申请日：2011-06-13

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L29/66

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US08551847B2

公开(公告)日：2013-10-08

申请号：US13070496

申请日：2011-03-24

Applicant: Chun-Yuan Wu ,  Chin-Cheng Chien ,  Chiu-Hsien Yeh ,  Yeng-Peng Wang

Inventor： Chun-Yuan Wu ,  Chin-Cheng Chien ,  Chiu-Hsien Yeh ,  Yeng-Peng Wang

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/26506 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for forming a metal gate is provided. First, a dummy material is formed to completely cover a substrate. Second, a dopant is selectively implanted into the dummy material. Then, some of the dummy material is removed to expose part of the substrate and to form a dummy gate including a dopant region disposed between a first region and a second region. Later an interlayer dielectric layer is formed to surround the dummy gate. Next, a selective etching step is carried out to remove the first region to form a recess without substantially removing the dopant region. Afterwards, the recess is filled with a material set to form a metal gate.

Abstract translation: 提供一种用于形成金属栅极的方法。 首先，形成虚拟材料以完全覆盖基板。 第二，将掺杂剂选择性地注入到虚拟材料中。 然后，去除一些虚拟材料以暴露部分衬底并形成包括设置在第一区域和第二区域之间的掺杂剂区域的虚拟栅极。 之后形成层间电介质层以包围虚拟栅极。 接下来，进行选择性蚀刻步骤以去除第一区域以形成凹部，而基本上不去除掺杂剂区域。 之后，用设置成形成金属门的材料填充凹部。

公开(公告)号：US08298950B2

公开(公告)日：2012-10-30

申请号：US12830370

申请日：2010-07-05

Applicant: Chan-Lon Yang ,  Yeng-Peng Wang ,  Chiu-Hsien Yeh

Inventor： Chan-Lon Yang ,  Yeng-Peng Wang ,  Chiu-Hsien Yeh

IPC: H01L21/311

CPC classification number: H01L21/823842 ,  H01L21/32134 ,  H01L21/32135 ,  H01L27/11 ,  H01L27/1104

Abstract: An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process.

Abstract translation: 蚀刻牺牲层的示例性方法包括以下步骤：提供形成有牺牲层并且由第一区域和第二区域限定的衬底，所述牺牲层设置在第一和第二区域中; 在暴露所述第二区域的同时形成覆盖所述第一区域的硬掩模; 在所述牺牲层上执行第一蚀刻工艺以使所述牺牲层变薄，同时形成覆盖所述薄化的牺牲层的副产物膜; 在副产品膜上执行第二蚀刻工艺以去除副产物层的一部分，用于暴露部分减薄的牺牲层，同时保留设置在减薄的牺牲层的侧壁上的副产物膜的另一部分; 以及对所述减薄的牺牲层执行第三蚀刻工艺，以去除在所述第二蚀刻工艺中暴露的所述薄化牺牲层的所述部分。

公开(公告)号：US20120244675A1

公开(公告)日：2012-09-27

申请号：US13070496

申请日：2011-03-24

Applicant: Chun-Yuan Wu ,  Chin-Cheng Chien ,  Chiu-Hsien Yeh ,  Yeng-Peng Wang

Inventor： Chun-Yuan Wu ,  Chin-Cheng Chien ,  Chiu-Hsien Yeh ,  Yeng-Peng Wang

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/26506 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for forming a metal gate is provided. First, a dummy material is formed to completely cover a substrate. Second, a dopant is selectively implanted into the dummy material. Then, some of the dummy material is removed to expose part of the substrate and to form a dummy gate including a dopant region disposed between a first region and a second region. Later an interlayer dielectric layer is formed to surround the dummy gate. Next, a selective etching step is carried out to remove the first region to form a recess without substantially removing the dopant region. Afterwards, the recess is filled with a material set to form a metal gate.

Abstract translation: 提供一种用于形成金属栅极的方法。 首先，形成虚拟材料以完全覆盖基板。 第二，将掺杂剂选择性地注入到虚拟材料中。 然后，去除一些虚拟材料以暴露部分衬底并形成包括设置在第一区域和第二区域之间的掺杂剂区域的虚拟栅极。 之后形成层间电介质层以包围虚拟栅极。 接下来，进行选择性蚀刻步骤以去除第一区域以形成凹部，而基本上不去除掺杂剂区域。 之后，用设置成形成金属门的材料填充凹部。

公开(公告)号：US20120003835A1

公开(公告)日：2012-01-05

申请号：US12830370

申请日：2010-07-05

Applicant: Chan-Lon YANG ,  Yeng-Peng Wang ,  Chiu-Hsien Yeh

Inventor： Chan-Lon YANG ,  Yeng-Peng Wang ,  Chiu-Hsien Yeh

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/823842 ,  H01L21/32134 ,  H01L21/32135 ,  H01L27/11 ,  H01L27/1104

Abstract: An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process.

Abstract translation: 蚀刻牺牲层的示例性方法包括以下步骤：提供形成有牺牲层并且由第一区域和第二区域限定的衬底，所述牺牲层设置在第一和第二区域中; 在暴露所述第二区域的同时形成覆盖所述第一区域的硬掩模; 在所述牺牲层上执行第一蚀刻工艺以使所述牺牲层变薄，同时形成覆盖所述薄化的牺牲层的副产物膜; 在副产品膜上执行第二蚀刻工艺以去除副产物层的一部分，用于暴露部分减薄的牺牲层，同时保留设置在减薄的牺牲层的侧壁上的副产物膜的另一部分; 以及对所述减薄的牺牲层执行第三蚀刻工艺，以去除在所述第二蚀刻工艺中暴露的所述薄化牺牲层的所述部分。

公开(公告)号：US07759252B2

公开(公告)日：2010-07-20

申请号：US11822754

申请日：2007-07-10

Applicant: Yeng-Peng Wang

Inventor： Yeng-Peng Wang

IPC: H01L21/302

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L27/10861

Abstract: The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.

Abstract translation: 本发明涉及两步背面蚀刻的方法。 首先，提供具有多个硬掩模的基板。 接下来，衬底的背面和边缘被背面蚀刻以去除衬底的背面和边缘上的硬掩模的部分。 然后，顺序地对硬掩模和衬底进行构图，以在衬底中形成多个沟槽。 最后，在进行湿浴步骤之前，对衬底的边缘进行背面蚀刻以去除衬底边缘上的针结构。

公开(公告)号：US08980753B2

公开(公告)日：2015-03-17

申请号：US12886580

申请日：2010-09-21

Applicant: Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

Inventor： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823814

Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

公开(公告)号：US20120070995A1

公开(公告)日：2012-03-22

申请号：US12886580

申请日：2010-09-21

Applicant: Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

Inventor： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

IPC: H01L21/302

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823814

Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

公开(公告)号：US20080280450A1

公开(公告)日：2008-11-13

申请号：US11822754

申请日：2007-07-10

Applicant: Yeng-Peng Wang

Inventor： Yeng-Peng Wang

IPC: H01L21/302

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L27/10861

Abstract: The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.

Abstract translation: 本发明涉及两步背面蚀刻的方法。 首先，提供具有多个硬掩模的基板。 接下来，衬底的背面和边缘被背面蚀刻以去除衬底的背面和边缘上的硬掩模的部分。 然后，顺序地对硬掩模和衬底进行构图，以在衬底中形成多个沟槽。 最后，在进行湿浴步骤之前，对衬底的边缘进行背面蚀刻以去除衬底边缘上的针结构。