公开(公告)号：US12040382B2

公开(公告)日：2024-07-16

申请号：US17322405

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chi Yu ,  Cheng-I Chu ,  Chen-Fong Tsai ,  Yi-Rui Chen ,  Sen-Hong Syue ,  Wen-Kai Lin ,  Yoh-Rong Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

公开(公告)号：US20240136428A1

公开(公告)日：2024-04-25

申请号：US18401833

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/78696 ,  H01L21/823468

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US20230268416A1

公开(公告)日：2023-08-24

申请号：US18311035

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/4983 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

公开(公告)号：US20230117574A1

公开(公告)日：2023-04-20

申请号：US17655208

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jin Li ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Wen-Kai Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure and a method of forming is provided. The semiconductor structure includes nanostructures separated from one another and stacked over a substrate, a gate stack wrapping around the nanostructures, and a dielectric fin structure laterally spaced apart from the nanostructures by the gate stack. The dielectric fin structure include a lining layer and a fill layer nested within the lining layer. The lining layer is made of a carbon-containing dielectric material, and a carbon concentration of the lining layer varies in a direction from the gate stack to the lining layer.

公开(公告)号：US20220262925A1

公开(公告)日：2022-08-18

申请号：US17322405

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chi Yu ,  Cheng-I Chu ,  Chen-Fong Tsai ,  Yi-Rui Chen ,  Sen-Hong Syue ,  Wen-Kai Lin ,  Yoh-Rong Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L21/8238

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

公开(公告)号：US20210376105A1

公开(公告)日：2021-12-02

申请号：US17145925

申请日：2021-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

公开(公告)号：US12206012B2

公开(公告)日：2025-01-21

申请号：US17333592

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

公开(公告)号：US20240194765A1

公开(公告)日：2024-06-13

申请号：US18425058

申请日：2024-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US12009407B2

公开(公告)日：2024-06-11

申请号：US18303841

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/0259 ,  H01L21/31116 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

公开(公告)号：US20230378256A1

公开(公告)日：2023-11-23

申请号：US17818057

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wen-Kai Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/41791 ,  H01L29/7851 ,  H01L21/823481 ,  H01L29/66545

Abstract: Transistor gate isolation structures and methods of forming the same are provided. In an embodiment, a device includes: an isolation region; a first gate structure on the isolation region; a second gate structure on the isolation region; and a gate isolation structure between the first gate structure and the second gate structure in a first cross-section, an upper portion of the gate isolation structure having a first concentration of an element, a lower portion of the gate isolation structure having a second concentration of the element, the first concentration different from the second concentration, the lower portion extending continuously along a sidewall of the first gate structure, beneath the upper portion, and along a sidewall of the second gate structure.