-
公开(公告)号：US12249592B2
公开(公告)日：2025-03-11
申请号：US17648236
申请日：2022-01-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Han-De Chen , Cheng-I Chu , Yun Chen Teng , Chen-Fong Tsai , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.
-
公开(公告)号：US20240266285A1
公开(公告)日：2024-08-08
申请号：US18639595
申请日：2024-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Fong Tsai , Cheng-I Chu , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
IPC: H01L23/528 , H01L23/367 , H01L23/46 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423
CPC classification number: H01L23/528 , H01L23/3672 , H01L23/46 , H01L29/401 , H01L29/41733 , H01L29/0665 , H01L29/42392
Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.
-
公开(公告)号：US12211820B2
公开(公告)日：2025-01-28
申请号：US17472086
申请日：2021-09-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Cheng-I Chu , Han-De Chen , Chen-Fong Tsai , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.
-
公开(公告)号：US20230019415A1
公开(公告)日：2023-01-19
申请号：US17648236
申请日：2022-01-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Han-De Chen , Cheng-I Chu , Yun Chen Teng , Chen-Fong Tsai , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.
-
公开(公告)号：US12040382B2
公开(公告)日：2024-07-16
申请号：US17322405
申请日：2021-05-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Li-Chi Yu , Cheng-I Chu , Chen-Fong Tsai , Yi-Rui Chen , Sen-Hong Syue , Wen-Kai Lin , Yoh-Rong Liu , Huicheng Chang , Yee-Chia Yeo
IPC: H01L29/66 , H01L21/02 , H01L21/285 , H01L21/306 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/786
CPC classification number: H01L29/66553 , H01L21/02236 , H01L21/0259 , H01L21/28518 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L27/092 , H01L29/0665 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/66636 , H01L29/66742 , H01L29/78618 , H01L29/78696
Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
-
Patent Agency Ranking
公开(公告)号：US20220359369A1
公开(公告)日：2022-11-10
申请号：US17381583
申请日：2021-07-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Fong Tsai , Cheng-I Chu , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
IPC: H01L23/528 , H01L29/417 , H01L23/367 , H01L23/46 , H01L29/40
Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.
-
公开(公告)号：US20220262925A1
公开(公告)日：2022-08-18
申请号：US17322405
申请日：2021-05-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Li-Chi Yu , Cheng-I Chu , Chen-Fong Tsai , Yi-Rui Chen , Sen-Hong Syue , Wen-Kai Lin , Yoh-Rong Liu , Huicheng Chang , Yee-Chia Yeo
IPC: H01L29/66 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/45 , H01L29/786 , H01L21/02 , H01L21/306 , H01L21/285 , H01L21/8238
Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
-
公开(公告)号：US20240387451A1
公开(公告)日：2024-11-21
申请号：US18786265
申请日：2024-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Cheng-I Chu , Han-De Chen , Chen-Fong Tsai , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.
-
公开(公告)号：US11990404B2
公开(公告)日：2024-05-21
申请号：US17381583
申请日：2021-07-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Fong Tsai , Cheng-I Chu , Jyh-Cherng Sheu , Huicheng Chang , Yee-Chia Yeo
IPC: H01L21/00 , H01L23/367 , H01L23/46 , H01L23/528 , H01L29/40 , H01L29/417 , H01L29/06 , H01L29/423
CPC classification number: H01L23/528 , H01L23/3672 , H01L23/46 , H01L29/401 , H01L29/41733 , H01L29/0665 , H01L29/42392
Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.
-
公开(公告)号：US20230163198A1
公开(公告)日：2023-05-25
申请号：US18151761
申请日：2023-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Li-Chi Yu , Cheng-I Chu , Chia-Hsuan Wang , Chen-Fong Tsai , Huicheng Chang , Yee-Chia Yeo
IPC: H01L29/66 , H01L29/08 , H01L29/786 , H01L29/06 , H01L21/8234
CPC classification number: H01L29/6656 , H01L29/0847 , H01L29/78696 , H01L29/0673 , H01L21/823412 , H01L21/823468 , H01L21/823418
Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxygen plasma treatment to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.017 seconds)
