公开(公告)号：US09899490B2

公开(公告)日：2018-02-20

申请号：US15014752

申请日：2016-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge

IPC: H01L29/775 ,  H01L29/786 ,  H01L21/335 ,  H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a nanowire structure formed over the substrate. In addition, the nanowire structure includes a first portion, a second portion, and a third portion. The semiconductor structure further includes a gate structure formed around the third portion of the nanowire structure and a source region formed in the first portion of the nanowire structure. In addition, a depletion region in the nanowire structure has a length longer than a length of the gate structure and is not in contact with the source region.

公开(公告)号：US09893189B2

公开(公告)日：2018-02-13

申请号：US15209224

申请日：2016-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02592 ,  H01L21/02636 ,  H01L21/02667 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

公开(公告)号：US09779959B2

公开(公告)日：2017-10-03

申请号：US14856875

申请日：2015-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/31

CPC classification number: H01L21/3085 ,  H01L21/31 ,  H01L21/311 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer.

公开(公告)号：US20160181429A1

公开(公告)日：2016-06-23

申请号：US15054925

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Wen-Hsing Hsieh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7856 ,  H01L21/823842 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer includes a first gate metal layer formed along both sides of the lower portion of the fin structure, the first gate metal layer having a first workfunction, and a second gate metal layer formed disposed over the first gate metal layer and wrapped around the upper portion of the fin structure, the second gate metal layer having a second workfunction. The first and the second workfunctions are different.

Abstract translation: 半导体器件包括具有翅片结构的衬底，鳍结构具有与衬底基本垂直的方向的高度，并且沿着高度具有连续的上部和下部，下部比上部更靠近衬底。 半导体器件还包括围绕鳍结构的一部分缠绕的栅极结构，栅极结构具有围绕鳍结构设置的栅介质层，以及设置在栅介电层上的栅电极层。 栅极电极层包括沿翅片结构的下部两侧形成的第一栅极金属层，第一栅极金属层具有第一功函数，第二栅极金属层形成在第一栅极金属层上并缠绕 鳍结构的上部，第二栅极金属层具有第二功函数。 第一个和第二个功能是不同的。

公开(公告)号：US08823060B1

公开(公告)日：2014-09-02

申请号：US13771249

申请日：2013-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

Abstract translation: 翅片内部的膨胀材料（通常为散热片半导体的氧化物）的FinFET导致在FinFET通道内显着增加电荷载流子迁移率的应变。 该概念可以应用于p型或n型FinFET。 对于p型FinFET，膨胀材料位于源极和漏极区域的下方。 对于n型FinFET，膨胀的材料位于通道区域的下方。 溶胀材料可以在源极和漏极区域具有或不具有应变诱导外延使用，并且可以提供比单独应变诱导外延可实现的更大的应变。

公开(公告)号：US20240387711A1

公开(公告)日：2024-11-21

申请号：US18788347

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H Diaz ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/477 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US11239084B2

公开(公告)日：2022-02-01

申请号：US16927942

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L21/285 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/306 ,  H01L29/45

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US11043597B2

公开(公告)日：2021-06-22

申请号：US16595580

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45

Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

公开(公告)号：US10714349B2

公开(公告)日：2020-07-14

申请号：US16370521

申请日：2019-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L29/417 ,  H01L21/306 ,  H01L29/45

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US20190393215A1

公开(公告)日：2019-12-26

申请号：US16559951

申请日：2019-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L21/822 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.