公开(公告)号：US10535680B2

公开(公告)日：2020-01-14

申请号：US15800390

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US10290546B2

公开(公告)日：2019-05-14

申请号：US15666715

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US20180151438A1

公开(公告)日：2018-05-31

申请号：US15666715

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US09941374B2

公开(公告)日：2018-04-10

申请号：US15362470

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Chung-Cheng Wu ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Jean-Pierre Colinge ,  Chun-Hsiung Lin ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/78 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/45 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

公开(公告)号：US20170077253A1

公开(公告)日：2017-03-16

申请号：US15362470

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Chung-Cheng Wu ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Jean-Pierre Colinge ,  Chun-Hsiung Lin ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC: H01L29/45 ,  H01L23/528 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L29/45 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain(S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract translation: 公开了一种半导体器件及其形成方法。 半导体器件包括衬底，第一和第二源极/漏极（S / D）区域，第一和第二S / D区域之间的沟道，与沟道接合的栅极以及连接到第一S / D区域的接触特征 。 接触特征包括第一和第二接触层。 第一接触层具有共形截面轮廓，并且在其至少两侧与第一S / D区域接触。 在实施例中，第一接触层与第一S / D区域的三个或四个侧面直接接触，以增加接触面积。 第一接触层包括半导体 - 金属合金，III-V半导体和锗中的一种。

公开(公告)号：US11955554B2

公开(公告)日：2024-04-09

申请号：US17812997

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/7848

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

公开(公告)号：US11581314B2

公开(公告)日：2023-02-14

申请号：US16723939

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Shu-Hui Sung ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Ting Yu Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US11139341B2

公开(公告)日：2021-10-05

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US10438851B2

公开(公告)日：2019-10-08

申请号：US16048581

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US20190006391A1

公开(公告)日：2019-01-03

申请号：US15800390

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/762

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.