公开(公告)号：US10720514B2

公开(公告)日：2020-07-21

申请号：US16104372

申请日：2018-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Gwan-Sin Chang ,  Yu-Ming Lin ,  Ching Hsueh ,  Jia-Chuan You ,  Chia-Hao Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor fin, a first gate stack, and a first metal element-containing dielectric mask. The semiconductor fin protrudes from the substrate. The first gate stack is over the semiconductor fin. The first metal element-containing dielectric mask is over the first gate stack.

公开(公告)号：US10056473B1

公开(公告)日：2018-08-21

申请号：US15481748

申请日：2017-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Gwan-Sin Chang ,  Yu-Ming Lin ,  Ching Hsueh ,  Jia-Chuan You ,  Chia-Hao Chang

IPC: H01L21/335 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7855

Abstract: A method for manufacturing a semiconductor device, including forming a dummy gate structure on a substrate, in which the substrate has a source/drain portion and a channel portion adjacent to the source/drain region, and the dummy gate structure is formed on the channel portion of the substrate; recessing at least a part of the source/drain portion to form a recess in the source/drain portion of the substrate; forming a stress material in the recess; replacing the dummy gate structure with a gate stack; removing the stress material in the recess after the replacing the dummy gate structure with the gate stack; and forming an epitaxy structure in the recess.

公开(公告)号：US11075282B2

公开(公告)日：2021-07-27

申请号：US16689033

申请日：2019-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Zhi-Qiang Wu ,  Chung-Cheng Wu ,  Chih-Han Lin ,  Gwan-Sin Chang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.

公开(公告)号：US12183805B2

公开(公告)日：2024-12-31

申请号：US17333676

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Li-Te Lin ,  Chung-Cheng Wu ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US11043579B2

公开(公告)日：2021-06-22

申请号：US16933100

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Gwan-Sin Chang ,  Yu-Ming Lin ,  Ching Hsueh ,  Jia-Chuan You ,  Chia-Hao Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/84

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin on a substrate. A dummy gate structure is formed crossing the semiconductor fin. The dummy gate structure is replaced with a metal gate structure. An epitaxial structure is formed in the semiconductor fin after replacing the dummy gate structure with the metal gate structure.

公开(公告)号：US20190386061A1

公开(公告)日：2019-12-19

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US12174545B2

公开(公告)日：2024-12-24

申请号：US18361254

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yu Chen ,  Sagar Deepak Khivsara ,  Kuo-An Liu ,  Chieh Hsieh ,  Shang-Chieh Chien ,  Gwan-Sin Chang ,  Kai Tak Lam ,  Li-Jui Chen ,  Heng-Hsin Liu ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: G03F7/00

Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.

公开(公告)号：US11201243B2

公开(公告)日：2021-12-14

申请号：US16559343

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Han-Yu Lin ,  Chun-Yu Chen ,  Chih-Ching Wang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

公开(公告)号：US11024721B2

公开(公告)日：2021-06-01

申请号：US16559369

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Li-Te Lin ,  Chung-Cheng Wu ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/49 ,  H01L29/40

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

公开(公告)号：US10510866B1

公开(公告)日：2019-12-17

申请号：US16007885

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Zhi-Qiang Wu ,  Chung-Cheng Wu ,  Chih-Han Lin ,  Gwan-Sin Chang

IPC: H01L29/66 ,  H01L27/08 ,  H01L21/02 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.