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公开(公告)号:US20160293547A1
公开(公告)日:2016-10-06
申请号:US15155539
申请日:2016-05-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangho Rha , Jongmin Baek , Wookyung You , Sanghoon Ahn , Nae-In Lee
IPC: H01L23/528 , H01L23/522 , H01L21/321 , H01L21/02 , H01L21/288 , H01L23/532 , H01L21/768
CPC classification number: H01L23/5283 , H01L21/02178 , H01L21/02274 , H01L21/0228 , H01L21/288 , H01L21/306 , H01L21/3212 , H01L21/76802 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76871 , H01L21/76877 , H01L21/76885 , H01L23/5222 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法可以包括在金属图案上和在绝缘层的相邻部分上形成覆盖层,所述覆盖层包括相对于所述绝缘层在所述金属图案上的第一蚀刻选择性,以及第二蚀刻层 在绝缘层的部分上相对于绝缘层的蚀刻选择性。 此外,该方法可以包括通过从绝缘层的部分去除覆盖层来形成与金属图案相邻的凹陷区域。 在从绝缘层的部分去除覆盖层之后,覆盖层的至少一部分可以保留在金属图案的最上表面上。 还提供了相关的半导体器件。
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公开(公告)号:US20240312903A1
公开(公告)日:2024-09-19
申请号:US18599910
申请日:2024-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangkoo Kang , Wookyung You , Koungmin Ryu , Hoonseok Seo , Woojin Lee
IPC: H01L23/522 , H01L23/48 , H01L23/528 , H01L29/417 , H01L29/775 , H01L29/786
CPC classification number: H01L23/5226 , H01L23/481 , H01L23/5283 , H01L23/5286 , H01L29/41733 , H01L29/775 , H01L29/78696
Abstract: Provided is a semiconductor device, the semiconductor device, including: a plurality of fin-type active patterns extending in a first direction on a substrate; a gate structure extending in a second direction, and crossing the plurality of fin-type active patterns; a plurality of separation structures extending in the second direction; source/drain regions disposed on the plurality of fin-type active patterns on both sides of the gate structure; an interlayer insulating layer covering the source/drain regions on the substrate; a contact structure connected to at least one of the source/drain regions; a buried conductive structure electrically connected to the contact structure in the interlayer insulating layer, and having a first width defined by a distance between adjacent separation structures among the plurality of separation structures; and a power transmission structure extending from the second surface toward the first surface of the substrate, and connected to the buried conductive structure.
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公开(公告)号:US11764149B2
公开(公告)日:2023-09-19
申请号:US17866782
申请日:2022-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Suhyun Bark , Kyeongbeom Park , Jongmin Baek , Jangho Lee , Wookyung You , Deokyoung Jung
IPC: H01L21/00 , H01L23/522 , H01L23/528 , H01L27/088
CPC classification number: H01L23/5226 , H01L23/528 , H01L27/088
Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
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公开(公告)号:US11133249B2
公开(公告)日:2021-09-28
申请号:US16877088
申请日:2020-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yeonggil Kim , Jongmin Baek , Wookyung You , Kyuhee Han
IPC: H01L23/522 , H01L21/768 , H01L23/528
Abstract: A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.
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公开(公告)号:US10186485B2
公开(公告)日:2019-01-22
申请号:US15897465
申请日:2018-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: VietHa Nguyen , Wookyung You , Inoue Naoya , Hak-Sun Lee , Byung-Kwon Cho , Songyi Han , Jongmin Baek , Jiwon Kang , Byunghee Kim , Young-Ju Park , Sanghoon Ahn , Jiwon Yun , Naein Lee , YoungWoo Cho
IPC: H01L23/48 , H01L23/532 , H01L23/522
Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
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公开(公告)号:US20180218980A1
公开(公告)日:2018-08-02
申请号:US15927270
申请日:2018-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangho Rha , Jongmin Beak , Wookyung You , Sanghoon Ahn , Nae-In Lee
IPC: H01L23/528 , H01L21/02 , H01L21/288 , H01L21/306 , H01L21/321 , H01L21/768 , H01L23/522 , H01L23/532
CPC classification number: H01L23/5283 , H01L21/02178 , H01L21/02274 , H01L21/0228 , H01L21/288 , H01L21/306 , H01L21/3212 , H01L21/76802 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76871 , H01L21/76877 , H01L21/76885 , H01L23/5222 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
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公开(公告)号:US20180174977A1
公开(公告)日:2018-06-21
申请号:US15897465
申请日:2018-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: VietHa Nguyen , Wookyung You , Inoue Naoya , Hak-Sun Lee , Byung-Kwon Cho , Songyi Han , Jongmin Baek , Jiwon Kang , Byunghee Kim , Young-Ju Park , Sanghoon Ahn , Jiwon Yun , Naein Lee , YoungWoo Cho
IPC: H01L23/532 , H01L23/522
CPC classification number: H01L23/53295 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L23/528 , H01L23/53238 , H01L23/53266
Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
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公开(公告)号:US20170170184A1
公开(公告)日:2017-06-15
申请号:US15357299
申请日:2016-11-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: VietHa Nguyen , Wookyung You , Inoue Naoya , Hak-Sun Lee , Byung-Kwon Cho , Songyi Han , Jongmin Baek , Jiwon Kang , Byunghee Kim , Young-Ju Park , Sanghoon Ahn , Jiwon Yun , Naein Lee , YoungWoo Cho
IPC: H01L27/105 , H01L29/06
CPC classification number: H01L23/53295 , H01L23/5222 , H01L23/53238 , H01L23/53266
Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
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公开(公告)号:US09406553B2
公开(公告)日:2016-08-02
申请号:US14595662
申请日:2015-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wookyung You , Sanghoon Ahn , Sangho Rha , Jongmin Baek , Nae-In Lee
IPC: H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/485
CPC classification number: H01L21/7682 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76837 , H01L21/76843 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L21/76879 , H01L23/485 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
Abstract translation: 半导体器件包括:包括第一区域和第二区域的衬底;布置在第一区域上并且彼此间隔开第一距离的第一导电图案;第二导电图案,设置在第二区域上并且彼此间隔开 第二距离大于第一距离,以及层间绝缘层,设置在第二导电图案之间并且包括具有对应于第一距离的宽度的至少一个凹部区域。
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30.
公开(公告)号:US20150287628A1
公开(公告)日:2015-10-08
申请号:US14595662
申请日:2015-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wookyung You , Sanghoon Ahn , Sangho Rha , Jongmin Baek , Nae-In Lee
IPC: H01L21/768 , H01L23/522 , H01L23/532 , H01L23/528
CPC classification number: H01L21/7682 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76837 , H01L21/76843 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L21/76879 , H01L23/485 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.
Abstract translation: 一种半导体器件包括:包括第一区域和第二区域的衬底;第一导电图案,设置在第一区域上并且彼此间隔开第一距离;第二导电图案,设置在第二区域上并且彼此间隔开 第二距离大于第一距离,以及层间绝缘层,设置在第二导电图案之间并且包括具有对应于第一距离的宽度的至少一个凹部区域。
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