公开(公告)号：US11764149B2

公开(公告)日：2023-09-19

申请号：US17866782

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US12014980B2

公开(公告)日：2024-06-18

申请号：US18446524

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US11424182B2

公开(公告)日：2022-08-23

申请号：US17130293

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US20210005551A1

公开(公告)日：2021-01-07

申请号：US16793366

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho LEE ,  Jongmin Baek ,  Wookyung YOU ,  Kyu-Hee HAN ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20220359379A1

公开(公告)日：2022-11-10

申请号：US17866782

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US11139244B2

公开(公告)日：2021-10-05

申请号：US16793366

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho Lee ,  Jongmin Baek ,  Wookyung You ,  Kyu-Hee Han ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20240030127A1

公开(公告)日：2024-01-25

申请号：US18446524

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US11776906B2

公开(公告)日：2023-10-03

申请号：US17480615

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho Lee ,  Jongmin Baek ,  Wookyung You ,  Kyu-Hee Han ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76832 ,  H01L21/76843 ,  H01L23/5226

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20210351123A1

公开(公告)日：2021-11-11

申请号：US17130293

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.