公开(公告)号：US09528949B2

公开(公告)日：2016-12-27

申请号：US14197737

申请日：2014-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Kim ,  Jin-A Ryu ,  Chang-Ho Lee ,  Dong-Won Kim ,  Jae-Ho Kim ,  Jung-Dae Park ,  Nae-Ry Yu ,  Pil-Kwon Jun

IPC: G01N23/20

CPC classification number: G01N23/20025 ,  G01N2223/611

Abstract: In a method of detecting inhomogeneity of a layer, an incident light may be irradiated to at least two regions of the layer at a first incident angle position. First reflected lights reflected from the two regions of the layer may be sensed. The incident light may be irradiated to the at least two regions of the layer at a second incident angle position. Second reflected lights reflected from the two regions of the layer may be sensed. The first reflected lights and the second reflected lights may be compared with each other to obtain the inhomogeneity of the layer. Thus, the layer having a spot may be found.

Abstract translation: 在检测层的不均匀性的方法中，入射光可以在第一入射角位置被照射到层的至少两个区域。 可以感测从层的两个区域反射的第一反射光。 可以在第二入射角位置将入射光照射到层的至少两个区域。 可以感测到从层的两个区域反射的第二反射光。 可以将第一反射光和第二反射光相互比较以获得层的不均匀性。 因此，可以发现具有斑点的层。

公开(公告)号：US09466703B2

公开(公告)日：2016-10-11

申请号：US14587411

申请日：2014-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hyun Song ,  Nak-Jin Son ,  Kwang-Seok Lee ,  Chang-Wook Jeong ,  Ui-Hui Kwon ,  Dong-Won Kim ,  Young-Kwan Park ,  Keun-Ho Lee

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/66803 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

Abstract translation: 提供一种制造半导体器件的方法。制造方法包括提供包括第一区域和第二区域的衬底，第一区域包括第一和第二子区域，第二区域包括第三和第四子区域，形成 在第一和第二区域上的第一至第四鳍片从基板突出，第一鳍片形成在第一子区域上，第二鳍片形成在第二子区域上，第三鳍片形成在第三子区域上， 并且所述第四鳍形成在所述第四子区域上，形成第一至第四虚拟栅极结构以与所述第一至第四鳍相交，所述第一伪栅极结构形成在所述第一鳍上，所述第二伪栅极结构形成在 第二鳍状物，第三伪栅极结构形成在第三鳍片上，第四伪栅极结构形成在第四鳍片上，在第一鳍片和第二鳍片中的每一个中形成第一掺杂区域 通过在第一和第二区域中同时进行离子注入工艺，通过在第一至第四虚拟栅极结构的两侧上将杂质掺杂到第一至第四鳍中，从而在第三和第四鳍片的每一个中掺杂第二掺杂区域; 以及去除第三鳍片的第一鳍片和第二掺杂区域的第一掺杂区域，或去除第四鳍片的第二鳍片和第二掺杂区域的第一掺杂区域。

公开(公告)号：US20140270078A1

公开(公告)日：2014-09-18

申请号：US14197737

申请日：2014-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Kim ,  Jin-A Ryu ,  Chang-Ho Lee ,  Dong-Won Kim ,  Jae-Ho Kim ,  Jung-Dae Park ,  Nae-Ry Yu ,  Pil-Kwon Jun

IPC: G01N23/20

CPC classification number: G01N23/20025 ,  G01N2223/611

Abstract: In a method of detecting inhomogeneity of a layer, an incident light may be irradiated to at least two regions of the layer at a first incident angle position. First reflected lights reflected from the two regions of the layer may be sensed. The incident light may be irradiated to the at least two regions of the layer at a second incident angle position. Second reflected lights reflected from the two regions of the layer may be sensed. The first reflected lights and the second reflected lights may be compared with each other to obtain the inhomogeneity of the layer. Thus, the layer having a spot may be found.

Abstract translation: 在检测层的不均匀性的方法中，入射光可以在第一入射角位置被照射到该层的至少两个区域。 可以感测从层的两个区域反射的第一反射光。 可以在第二入射角位置将入射光照射到层的至少两个区域。 可以感测到从层的两个区域反射的第二反射光。 可以将第一反射光和第二反射光相互比较以获得层的不均匀性。 因此，可以发现具有斑点的层。

公开(公告)号：US20130224925A1

公开(公告)日：2013-08-29

申请号：US13854322

申请日：2013-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Ming Li ,  Sung-Hwan Kim

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Abstract translation: 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US12227891B2

公开(公告)日：2025-02-18

申请号：US18517198

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baek Gyu Kwon ,  Dong-Won Kim ,  Do Yun Lee ,  Bo-Kyun Kim ,  Geon Ho Lee

IPC: D06F37/22 ,  D06F21/04 ,  D06F21/08 ,  D06F31/00 ,  D06F37/20 ,  D06F37/26 ,  D06F39/12

Abstract: A washing machine including a plurality of washers may include a fixing bracket coupled to a front of a first housing in which a first tub is disposed and a front of a second housing in which a second tub is disposed, to prevent the first housing and the second housing from being separated from each other.

公开(公告)号：US09673099B2

公开(公告)日：2017-06-06

申请号：US15136450

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L21/8234 ,  H01L29/775 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US09331199B2

公开(公告)日：2016-05-03

申请号：US14667810

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Hwi Cho ,  Sung-Il Park ,  Byoung-Hak Hong ,  Toshinori Fukai ,  Mun-Hyeon Kim ,  Woong-Gi Kim ,  Sue-Hye Park ,  Dong-Won Kim ,  Dae-Won Ha

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7845 ,  H01L21/28123 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Abstract translation: 提供了一种应用了用于性能改进的图案结构的半导体器件。 所述半导体器件包括在第一方向上彼此间隔开的第一和第二有源区，隔着隔离层彼此隔开的第一正常栅极，形成在第一有源区上以沿与第一方向交叉的第二方向延伸的第一正常栅极，第一伪栅极 具有与所述隔离层的一端重叠的部分，并且所述另一部分与所述第一有源区域重叠并且在所述第一方向上与所述第一正常栅极间隔开，第二伪栅极具有与所述隔离层的另一端重叠的部分 并且另一部分与第二有源区重叠，形成在第一正常栅极和第一伪栅极之间的源极/漏极区域上的第一正常源极/漏极接触器和形成在隔离层上以使得不重叠的虚拟接触 与第一和第二伪栅极并且具有与第一正常源极/漏极接触件不同的尺寸。

公开(公告)号：US09324850B2

公开(公告)日：2016-04-26

申请号：US14162052

申请日：2014-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Abstract translation: 集成电路器件包括第一晶体管，其具有在第一源极/漏极之间的第一沟道和在第二源极/漏极之间具有第二沟道的第二晶体管。 第一晶体管基于第一电流量而工作，并且第二晶体管基于不同于第一电流量的第二电流量来操作。 第一和第二通道具有固定的通道宽度。 固定通道宽度可以基于包括在第一和第二晶体管中的翅片或纳米线。

公开(公告)号：US20140322882A1

公开(公告)日：2014-10-30

申请号：US13870471

申请日：2013-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mark S. Rodder ,  Dong-Won Kim

IPC: H01L29/10 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7856

Abstract: Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin.

Abstract translation: 提供了形成鳍状场效应晶体管（FinFET）的方法。 所述方法可以包括使用掩模来将源极/漏极延伸区掺杂物选择性地并入到半导体鳍片的源极和漏极区域中，以阻止源极/漏极延伸区掺杂物掺入到半导体鳍片的至少部分中。 所述方法可以包括去除半导体鳍片的源区和漏区的部分以在其中限定凹陷。 所述方法可以包括从半导体鳍片中的凹部外延生长源极和漏极区域。