公开(公告)号：US09331199B2

公开(公告)日：2016-05-03

申请号：US14667810

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Hwi Cho ,  Sung-Il Park ,  Byoung-Hak Hong ,  Toshinori Fukai ,  Mun-Hyeon Kim ,  Woong-Gi Kim ,  Sue-Hye Park ,  Dong-Won Kim ,  Dae-Won Ha

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7845 ,  H01L21/28123 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Abstract translation: 提供了一种应用了用于性能改进的图案结构的半导体器件。 所述半导体器件包括在第一方向上彼此间隔开的第一和第二有源区，隔着隔离层彼此隔开的第一正常栅极，形成在第一有源区上以沿与第一方向交叉的第二方向延伸的第一正常栅极，第一伪栅极 具有与所述隔离层的一端重叠的部分，并且所述另一部分与所述第一有源区域重叠并且在所述第一方向上与所述第一正常栅极间隔开，第二伪栅极具有与所述隔离层的另一端重叠的部分 并且另一部分与第二有源区重叠，形成在第一正常栅极和第一伪栅极之间的源极/漏极区域上的第一正常源极/漏极接触器和形成在隔离层上以使得不重叠的虚拟接触 与第一和第二伪栅极并且具有与第一正常源极/漏极接触件不同的尺寸。

公开(公告)号：US10978453B2

公开(公告)日：2021-04-13

申请号：US16205481

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Won Ha ,  Byoung-Hak Hong

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/165 ,  H01L21/02 ,  H01L21/266 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.

公开(公告)号：US10177148B2

公开(公告)日：2019-01-08

申请号：US15434177

申请日：2017-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Won Ha ,  Byoung-Hak Hong

IPC: H01L21/84 ,  H01L21/266 ,  H01L21/82 ,  H01L29/78 ,  H01L29/417 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.

公开(公告)号：US20140225169A1

公开(公告)日：2014-08-14

申请号：US13832017

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Dae-Won Ha ,  Su-Yeon Park

IPC: H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: A gate all around (GAA) type semiconductor device is provided. The GAA type semiconductor device includes source/drain layers formed to be spaced apart from each other, a channel layer connecting the source/drain layers, and a gate electrode formed along the periphery of at least a portion of the channel layer, wherein lower portions of the source/drain layers are formed more deeply than the channel layer, and an insulation pattern is formed between the lower portions of the source/drain layers and lower portions of the gate electrode.

Abstract translation: 提供了全封闭（GAA）型半导体器件。 GAA型半导体器件包括形成为彼此间隔开的源极/漏极层，连接源极/漏极层的沟道层以及沿着沟道层的至少一部分的周边形成的栅电极，其中下部 源极/漏极层的沟道层比沟道层更深地形成，并且在源/漏层的下部和栅电极的下部之间形成绝缘图案。

公开(公告)号：US09711505B2

公开(公告)日：2017-07-18

申请号：US15094282

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Hak Hong ,  Bon-Woong Koo ,  Sung-Il Park ,  Kyu-Baik Chang ,  Keun-Hwi Cho ,  Dae-Won Ha

IPC: H01L23/52 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.

公开(公告)号：US11894376B2

公开(公告)日：2024-02-06

申请号：US17197496

申请日：2021-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Won Ha ,  Byoung-Hak Hong

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/02192 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7846 ,  H01L29/7854 ,  H01L29/513 ,  H01L29/517

Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.

公开(公告)号：US20160043222A1

公开(公告)日：2016-02-11

申请号：US14667810

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Hwi Cho ,  Sung-II Park ,  Byoung-Hak Hong ,  Toshinori Fukai ,  Mun-Hyeon Kim ,  Woong-Gi Kim ,  Sue-Hye Park ,  Dong-Won Kim ,  Dae-Won Ha

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/28123 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Abstract translation: 提供了一种应用了用于性能改进的图案结构的半导体器件。 所述半导体器件包括在第一方向上彼此间隔开的第一和第二有源区，隔着隔离层彼此隔开的第一正常栅极，形成在第一有源区上以沿与第一方向交叉的第二方向延伸的第一正常栅极，第一伪栅极 具有与所述隔离层的一端重叠的部分，并且所述另一部分与所述第一有源区域重叠并且在所述第一方向上与所述第一正常栅极间隔开，第二伪栅极具有与所述隔离层的另一端重叠的部分 并且另一部分与第二有源区重叠，形成在第一正常栅极和第一伪栅极之间的源极/漏极区域上的第一正常源极/漏极接触器和形成在隔离层上以使得不重叠的虚拟接触 与第一和第二伪栅极并且具有与第一正常源极/漏极接触件不同的尺寸。