公开(公告)号：US09331199B2

公开(公告)日：2016-05-03

申请号：US14667810

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Hwi Cho ,  Sung-Il Park ,  Byoung-Hak Hong ,  Toshinori Fukai ,  Mun-Hyeon Kim ,  Woong-Gi Kim ,  Sue-Hye Park ,  Dong-Won Kim ,  Dae-Won Ha

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7845 ,  H01L21/28123 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Abstract translation: 提供了一种应用了用于性能改进的图案结构的半导体器件。 所述半导体器件包括在第一方向上彼此间隔开的第一和第二有源区，隔着隔离层彼此隔开的第一正常栅极，形成在第一有源区上以沿与第一方向交叉的第二方向延伸的第一正常栅极，第一伪栅极 具有与所述隔离层的一端重叠的部分，并且所述另一部分与所述第一有源区域重叠并且在所述第一方向上与所述第一正常栅极间隔开，第二伪栅极具有与所述隔离层的另一端重叠的部分 并且另一部分与第二有源区重叠，形成在第一正常栅极和第一伪栅极之间的源极/漏极区域上的第一正常源极/漏极接触器和形成在隔离层上以使得不重叠的虚拟接触 与第一和第二伪栅极并且具有与第一正常源极/漏极接触件不同的尺寸。

公开(公告)号：US09966376B2

公开(公告)日：2018-05-08

申请号：US15231134

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mun-Hyeon Kim ,  Chang-Woo Noh ,  Keun-Hwi Cho ,  Myung-Gil Kang ,  Shigenobu Maeda

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

公开(公告)号：US20160043222A1

公开(公告)日：2016-02-11

申请号：US14667810

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Hwi Cho ,  Sung-II Park ,  Byoung-Hak Hong ,  Toshinori Fukai ,  Mun-Hyeon Kim ,  Woong-Gi Kim ,  Sue-Hye Park ,  Dong-Won Kim ,  Dae-Won Ha

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/28123 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Abstract translation: 提供了一种应用了用于性能改进的图案结构的半导体器件。 所述半导体器件包括在第一方向上彼此间隔开的第一和第二有源区，隔着隔离层彼此隔开的第一正常栅极，形成在第一有源区上以沿与第一方向交叉的第二方向延伸的第一正常栅极，第一伪栅极 具有与所述隔离层的一端重叠的部分，并且所述另一部分与所述第一有源区域重叠并且在所述第一方向上与所述第一正常栅极间隔开，第二伪栅极具有与所述隔离层的另一端重叠的部分 并且另一部分与第二有源区重叠，形成在第一正常栅极和第一伪栅极之间的源极/漏极区域上的第一正常源极/漏极接触器和形成在隔离层上以使得不重叠的虚拟接触 与第一和第二伪栅极并且具有与第一正常源极/漏极接触件不同的尺寸。