公开(公告)号：US09853112B2

公开(公告)日：2017-12-26

申请号：US14802479

申请日：2015-07-17

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/538 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/304 ,  H01L27/02

CPC classification number: H01L29/4238 ,  G06F17/5077 ,  H01L21/3043 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

公开(公告)号：US09806083B2

公开(公告)日：2017-10-31

申请号：US14559205

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  G11C5/06 ,  G11C8/14 ,  G11C11/412 ,  H01L21/768 ,  G11C8/16 ,  G11C11/418 ,  H01L27/02

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

公开(公告)号：US20170236841A1

公开(公告)日：2017-08-17

申请号：US15160192

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Jeffrey Junhao Xu ,  Kern Rim ,  Vladimir Machkaoutsan

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/267 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/785

Abstract: A device includes a substrate, a fin, and an isolation layer. The device also includes an epitaxial cladding layer on a sidewall of the fin. The epitaxial cladding layer has a substantially uniform thickness and has a continuous lattice structure at an interface with the sidewall. The epitaxial cladding layer is positioned above the isolation layer.

公开(公告)号：US20170074728A1

公开(公告)日：2017-03-16

申请号：US14856004

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Kern Rim

IPC: G01K7/01 ,  H01L27/092

CPC classification number: G01K7/015 ,  H01L27/0924 ,  H01L29/78606

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

Abstract translation: 器件包括源极接触，漏极接触，栅极接触和身体接触。 身体接触件电耦合到温度感测电路。 源极触点，漏极接触，栅极接触和主体接触包括在鳍状场效应晶体管（finFET）中。

公开(公告)号：US20170018620A1

公开(公告)日：2017-01-19

申请号：US14802479

申请日：2015-07-17

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/304 ,  H01L29/66 ,  G06F17/50 ,  H01L21/8238

CPC classification number: H01L29/4238 ,  G06F17/5077 ,  H01L21/3043 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

Abstract translation: 一种制造器件的方法包括执行栅极切割以切割栅极线以产生第一栅极区域和第二栅极区域。 该方法还包括沉积导电材料以形成导电跳线结构以连接第一栅区和第二栅区。

公开(公告)号：US20160163713A1

公开(公告)日：2016-06-09

申请号：US14559205

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

Abstract translation: 公开了在单独的金属层上具有字线的静态随机存取存储器（SRAM）位单元，以提高性能。 在一个方面，公开了采用第二金属层中的写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线增加宽度，这降低了字线电阻，减少了访问时间，并提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨迹。 为了将读取的字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在设置在第一金属层中的相应的轨道上。 对应于写入字线的着陆垫被放置在设置在第一金属层中的对应的轨道上。

公开(公告)号：US20160141021A1

公开(公告)日：2016-05-19

申请号：US14546980

申请日：2014-11-18

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

公开(公告)号：US20160079175A1

公开(公告)日：2016-03-17

申请号：US14484366

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53257 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

Abstract translation: 公开了采用使用细长通孔的金属线的局部互连的中线（MOL）制造的集成电路（IC）。 还公开了相关方法。 特别地，金属层中的不同金属线可能需要在IC的MOL工艺期间电连接。 在这方面，为了允许金属线互连，而不在例如在示例性方面中在印刷过程中难以提供的金属线上方提供这样的互连，在一个或多个金属线中提供细长或扩张的通孔 IC中的MOL层。 细长通道设置在MOL层中的金属层下方的MOL层中，并且延伸穿过MOL层的金属层中的两个或更多个相邻的金属层。 移动MOL层上方的互连可以简化IC的制造，特别是在纳米（nm）节点尺寸较小的情况下。

公开(公告)号：US20160027726A1

公开(公告)日：2016-01-28

申请号：US14444104

申请日：2014-07-28

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Choh Fei Yeap ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/528 ,  H01L21/321 ,  H01L21/311 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

Abstract translation: 一种装置包括第一互连和第一屏障结构。 第一阻挡结构与电介质材料接触。 该装置还包括与第一阻挡结构和蚀刻停止层接触的第一保护结构。 至少部分地由第一保护结构和蚀刻停止层限定气隙。

公开(公告)号：US20150255571A1

公开(公告)日：2015-09-10

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract translation: 在特定实施例中，一种方法包括在半导体器件的伪栅极上形成第一间隔结构，并在第一间隔物结构上形成牺牲隔离物。 该方法还包括蚀刻半导体器件的结构以形成开口，经由开口去除牺牲隔离物，以及沉积材料以限定间隙。