公开(公告)号：US20160314235A1

公开(公告)日：2016-10-27

申请号：US14693690

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F7/70433 ,  G06F17/5068 ,  G06F17/5081 ,  H01L27/0207

Abstract: A circuit layout data has a start value of a first-axis pitch and a start value of a second-axis pitch, the second axis pitch being transverse to the first-axis pitch. The start value of the first axis pitch and the start value of the second axis pitch correspond to single pattern lithography. The first axis pitch is scaled to a first axis single pattern-to-double pattern pitch transition threshold, and then additionally scaled until reaching a first axis double pattern resolution limit. Scaling the first axis pitch to the first axis double pattern resolution limit utilizes routing spaces parallel to the second axis pitch.

Abstract translation: 电路布局数据具有第一轴节距的起始值和第二轴节距的起始值，第二轴节距横向于第一轴节距。 第一轴距的开始值和第二轴距的开始值对应于单模式光刻。 第一轴音调被缩放到第一轴单一图案到双重图案间距转换阈值，然后另外缩放直到达到第一轴双重图案分辨率极限。 将第一轴距调整为第一轴双重图案分辨率极限利用与第二轴距平行的路线空间。

公开(公告)号：US20160284595A1

公开(公告)日：2016-09-29

申请号：US14670314

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Chunqi GENG ,  Choh Fei YEAP ,  Stanley Seungchul SONG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor chip includes a circuit block. The circuit block includes a first transistor(s) having an enhanced first performance characteristic different from a second performance characteristic of a second transistor(s) of the circuit block. The circuit block also includes a marker layer to identify the first transistor(s).

Abstract translation: 半导体芯片包括电路块。 电路块包括具有与电路块的第二晶体管的第二性能特性不同的增强的第一性能特性的第一晶体管。 电路块还包括标识层以识别第一晶体管。

公开(公告)号：US20160211216A1

公开(公告)日：2016-07-21

申请号：US14819159

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing BAO ,  John Jianhong ZHU ,  Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Choh Fei YEAP

IPC: H01L23/532 ,  G05B19/418 ,  H01L21/768 ,  B29C67/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

Abstract translation: 集成电路器件包括包括铝的第一金属层。 集成电路器件包括具有互连结构的第二金属层。 互连结构包括一层包括铝的第一材料。 集成电路器件包括包括铝的互扩散层。 互扩散层靠近第一金属层并且靠近包括铝的第一材料层。 集成电路器件包括包含铝的自形成阻挡层。 自形成阻挡层靠近电介质层并且靠近包括铝的第一材料层。

公开(公告)号：US20160181161A1

公开(公告)日：2016-06-23

申请号：US14581244

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7851

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active potion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract translation: 鳍状结构可以包括半导体衬底的表面上的翅片。 每个翅片可以包括靠近半导体衬底的表面的掺杂部分。 鳍状结构还可以包括设置在散热片之间和半导体衬底的表面上的隔离层。 鳍状结构还可以包括在散热片的掺杂部分的侧壁上的凹陷的隔离衬垫。 翅片的无衬里的掺杂部分可以从凹入的隔离衬垫延伸到隔离层的表面处的翅片的活性部分。 隔离层设置在翅片的无衬里的掺杂部分上。

公开(公告)号：US20160133722A1

公开(公告)日：2016-05-12

申请号：US15000127

申请日：2016-01-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/762 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L29/66651 ,  H01L21/28035 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

Abstract: A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.

公开(公告)号：US20160093511A1

公开(公告)日：2016-03-31

申请号：US14496365

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Samit SENGUPTA ,  Shashank EKBOTE ,  Da YANG ,  Choh Fei YEAP

IPC: H01L21/3213 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886

Abstract: A multigate transistor device such as a fin-shaped field effect transistor (FinFET) is fabricated by applying a self-aligned diffusion break (SADB) mask having an opening positioned to expose an area of at least one portion of at least one gate stripe designated as at least one tie-off gate in the multigate transistor device and removing the tie-off gate through the opening of the SADB mask to isolate transistors adjacent to the tie-off gate.

Abstract translation: 通过施加具有开口的自对准扩散断裂（SADB）掩模来制造诸如鳍状场效应晶体管（FinFET）的多栅晶体管器件，所述掩模被定位成暴露指定的至少一个栅极条的至少一部分的区域 作为多栅极晶体管器件中的至少一个截止栅极，并且通过SADB掩模的开口去除关断栅极，以隔离与截止栅极相邻的晶体管。

公开(公告)号：US20160005822A1

公开(公告)日：2016-01-07

申请号：US14321568

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Kern RIM ,  Zhongze WANG

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to a three-terminal semiconductor device including a self-aligned via for connecting to a gate terminal Hardmasks and spacers formed over top portions and sidewall portions of a drain connection to a drain terminal and a source connection to a source terminal protect and insulate the drain connection and the source connection, such that short circuits are avoided between the source and drain connections and the self-aligned via. The self-aligned via provides a direct metal-gate connection path between the gate terminal and a metal line such as a M1 metal line while avoiding a separate gate connection layer.

Abstract translation: 系统和方法涉及三端子半导体器件，其包括用于连接到栅极端子的自对准通孔。硬掩模和形成在到漏极端子的漏极连接的顶部和侧壁部分上的间隔物以及到源极端子的源极连接 保护和绝缘漏极连接和源极连接，从而避免在源极和漏极连接和自对准通孔之间产生短路。 自对准通孔在栅极端子和诸如M1金属线的金属线之间提供直接的金属栅极连接路径，同时避免了单独的栅极连接层。

公开(公告)号：US20150235948A1

公开(公告)日：2015-08-20

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Ohsang KWON ,  Kern RIM ,  John Jianhong ZHU ,  Xiangdong CHEN ,  Foua VANG ,  Raymond George STEPHANY ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20150194525A1

公开(公告)日：2015-07-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。