公开(公告)号：US20170287831A1

公开(公告)日：2017-10-05

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20150340353A1

公开(公告)日：2015-11-26

申请号：US14818902

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract translation: 本文通常描述用于局部高密度衬底布线的系统和方法的实施例。 在一个或多个实施例中，一种装置包括介质，第一和第二电路元件，互连元件和电介质层。 该介质可以包括其中的低密度路由。 互连元件可以嵌入在介质中，并且可以在其中包括多个导电构件，导电构件可以电耦合到第一电路元件和第二电路元件。 互连元件可以包括其中的高密度路由。 电介质层可以在互连裸片上方，电介质层包括通过其中的第一和第二电路元件。

公开(公告)号：US09001520B2

公开(公告)日：2015-04-07

申请号：US13625406

申请日：2012-09-24

Applicant: Intel Corporation

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/15 ,  H01L23/538 ,  H01L23/00 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

Abstract translation: 本说明书的实施例涉及制造微电子结构的领域。 微电子结构可以包括与轨迹路由结构分开形成的玻璃布线结构，其中玻璃布线结构以层叠或嵌入的形式结合到迹线布线基板中。 还公开了微电子封装的实施例，其包括设置在微电子衬底的玻璃布线结构附近并通过多个互连与微电子衬底耦合的至少一个微电子器件。 此外，公开了微电子结构的实施例，其包括嵌入微电子密封剂内的至少一个微电子器件，该微电子器件具有连接到微电子密封剂的玻璃布线结构和形成在玻璃布线结构上的迹线布线结构。

公开(公告)号：US10763215B2

公开(公告)日：2020-09-01

申请号：US15774221

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Robert L. Sankman ,  Scott M. Mokler ,  Richard C. Stamey

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.

公开(公告)号：US10366951B2

公开(公告)日：2019-07-30

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20190057937A1

公开(公告)日：2019-02-21

申请号：US15774221

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Robert L. Sankman ,  Scott M. Mokler ,  Richard C. Stamey

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2221/68345

Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.

公开(公告)号：US20190057915A1

公开(公告)日：2019-02-21

申请号：US16080093

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Robert L. Sankman ,  Scott M. Mokler ,  Richard Christopher Stamey ,  Amruthavalli Pallavi Alur

IPC: H01L23/13 ,  H01L23/538 ,  H01L23/498

Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.

公开(公告)号：US20180350737A1

公开(公告)日：2018-12-06

申请号：US16002740

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US10008452B2

公开(公告)日：2018-06-26

申请号：US15469964

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H01L29/40 ,  H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

公开(公告)号：US20180134547A1

公开(公告)日：2018-05-17

申请号：US15354761

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Amanuel M. Abebaw ,  Liwei Wang ,  Mark Saltas ,  Sandeep S. Iyer ,  Nick Labanok

IPC: B81C1/00 ,  B29C65/48 ,  B29C65/14 ,  B81B3/00

CPC classification number: B81C1/00182 ,  B29C65/14 ,  B29C65/4805 ,  B29L2031/34 ,  B81B3/0032 ,  B81B3/0051 ,  B81B3/0054 ,  B81B3/0059 ,  B81B3/0062 ,  B81B2201/038 ,  B81B2201/042 ,  B81B2203/0163 ,  B81B2203/051 ,  B81C2203/032

Abstract: Apparatuses, systems, and methods associated with placement of magnets within a microelectromechanical system device are disclosed herein. In embodiments, a method of affixing at least one magnet in a microelectromechanical system, may include affixing an electromagnetic actuator to a base structure of the microelectromechanical system, the affixing including affixing the electromagnetic actuator within a recess formed in the base structure. The method may further include placing a magnet within the recess, wherein the recess includes at least a portion of a spring, the spring affixed to the base structure and extending into the recess, the placing including placing the magnet on a side of the electromagnetic actuator, between the spring and the side of the electromagnetic actuator, the spring pressing the magnet against the side of the electromagnetic actuator and maintaining a position of the magnet in response to the placing the magnet within the recess.