公开(公告)号：US20200294924A1

公开(公告)日：2020-09-17

申请号：US16889190

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/13 ,  H05K1/14 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US10121701B2

公开(公告)日：2018-11-06

申请号：US15220143

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Mark Hlad

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/36 ,  H01L23/48 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H05K3/46

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

公开(公告)号：US20160133552A1

公开(公告)日：2016-05-12

申请号：US14992535

申请日：2016-01-11

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。

公开(公告)号：US09236366B2

公开(公告)日：2016-01-12

申请号：US13722203

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stephanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H05K3/40 ,  H01L25/065 ,  H01L23/14 ,  H01L23/538 ,  H05K1/03 ,  H05K1/14 ,  H05K3/46 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。

公开(公告)号：US09111916B2

公开(公告)日：2015-08-18

申请号：US14194936

申请日：2014-03-03

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H05K3/46 ,  H05K3/40 ,  H01L23/00 ,  H05K3/00

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15312 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2203/0769 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract translation: 无芯针脚阵列（PGA）衬底包括不使用焊料与PGA衬底集成的PGA引脚。 通过在PGA引脚上形成积聚层，使无芯PGA基板集成PGA引脚的过程，使得通孔与PGA引脚的引脚头直接接触。

公开(公告)号：US08928151B2

公开(公告)日：2015-01-06

申请号：US14019759

申请日：2013-09-06

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Islam Salama ,  Yonggang Li

IPC: H01L23/48 ,  H01L23/498

CPC classification number: H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract translation: 半导体器件基板包括前部和后部，其是设置在第一芯的前表面和后表面上的层叠芯。 第一芯具有圆柱形电镀通孔，其已被金属电镀并填充有空芯材料。 前部和后部具有激光钻孔的锥形通孔，其填充有导电材料并且连接到电镀通孔。 后部包括与前部连通的整体电感线圈。 第一芯和层叠芯形成具有集成电感线圈的混合芯半导体器件衬底。

公开(公告)号：US20190355636A1

公开(公告)日：2019-11-21

申请号：US16526497

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US10410939B2

公开(公告)日：2019-09-10

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/52 ,  H01L23/12 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20190051447A1

公开(公告)日：2019-02-14

申请号：US16162465

申请日：2018-10-17

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Yikang Deng

IPC: H01F27/28 ,  H01F27/255 ,  C25D5/48 ,  H01F41/04 ,  H01F41/02 ,  C25D5/16 ,  H01F17/00 ,  C25D7/00

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

公开(公告)号：US10085341B2

公开(公告)日：2018-09-25

申请号：US15461406

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K7/10 ,  H05K1/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/20 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.