公开(公告)号：US20140170533A1

公开(公告)日：2014-06-19

申请号：US13719621

申请日：2012-12-19

申请人： GLOBAL FOUNDRIES INC. ,  SEMATECH, INC.

发明人： Lei Sun ,  Pawitter S. Mangat ,  Vibhu Jindal ,  Obert R. Wood, II

IPC分类号： G03F1/22

CPC分类号： G03F1/22

摘要： An alternating phase shift mask for use with extreme ultraviolet lithography is provided. A substrate with a planar top surface is used as a base for the phase shift mask. A spacer layer serves as a Fabry-Perot cavity for controlling the phase shift difference between two adjacent surfaces of the phase shift mask and controlling the reflectivity from the top of the second multilayer. A protective layer serves as an etch stop layer to protect a first multilayer region in certain regions of the phase shift mask, while other regions of the phase shift mask utilize a second multilayer region for achieving a phase shift difference. Some embodiments may further include an absorber layer region to provide areas with no reflectance, in addition to the areas of alternating phase shift. Embodiments of the present invention may be used to monitor the focus and aberration of a lithography tool.

摘要翻译： 提供了一种用于极紫外光刻的交替相移掩模。 具有平面顶表面的基板用作相移掩模的基底。 间隔层用作法布里 - 珀罗腔，用于控制相移掩模的两个相邻表面之间的相移差，并控制来自第二多层的顶部的反射率。 保护层用作蚀刻停止层以保护相移掩模的某些区域中的第一多层区域，而相移掩模的其它区域利用第二多层区域来实现相移差。 除了交替相移的区域之外，一些实施例还可以包括提供没有反射率的区域的吸收层区域。 本发明的实施例可以用于监测光刻工具的焦点和像差。

公开(公告)号：US20140131809A1

公开(公告)日：2014-05-15

申请号：US13676575

申请日：2012-11-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBAL FOUNDRIES INC

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan

IPC分类号： H01L21/02 ,  H01L27/092

CPC分类号： H01L27/0922 ,  H01L21/02697 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal.

摘要翻译： 一种制造用于CMOS器件的替代金属栅极结构的方法，包括在CMOS器件的nFET部分和pFET部分上形成伪栅极结构; 在所述虚拟栅极结构之间沉积层间电介质; 从nFET和pFET部分去除伪栅极结构，导致nFET部分上的凹槽和pFET部分上的凹陷; 将栅电介质共形沉积在nFET和pFET部分上的凹槽中; 将第一氮化钛，氮化钽和第二氮化钛的顺序层沉积到nFET和pFET部分上的凹槽中; 仅从nFET部分去除第二层氮化钛; 将第三层氮化钛沉积到nFET和pFET部分上的凹槽中; 并用金属填充nFET和pFET部分上的空腔的其余部分。

公开(公告)号：US20140131735A1

公开(公告)日：2014-05-15

申请号：US13678124

申请日：2012-11-15

申请人： GLOBAL FOUNDRIES INC.

发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Illgen

IPC分类号： H01L29/78 ,  H01L29/16

CPC分类号： H01L21/2257 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66628

摘要： A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.

摘要翻译： 一种方法包括提供包括衬底，在衬底上的电绝缘层和电绝缘层上的半导体特征的半导体结构。 在半导体特征上形成栅极结构。 原位掺杂的半导体材料沉积在与栅极结构相邻的半导体器件的部分上。 掺杂剂从原位掺杂的半导体材料扩散到与栅极结构相邻的半导体器件的部分，掺杂剂扩散到半导体器件的与栅极结构相邻的部分，形成半导体器件中的掺杂源极和漏极区。

公开(公告)号：US20130334604A1

公开(公告)日：2013-12-19

申请号：US13968545

申请日：2013-08-16

申请人： GLOBAL FOUNDRIES Inc.

发明人： Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/1207

摘要： When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

摘要翻译： 当形成复杂的SOI器件时，通过使用一个相同的注入掩模来形成衬底二极管和膜二极管，以确定相应阱区中的阱掺杂剂浓度。 因此，在进一步处理期间，可以独立于半导体层中的二极管的阱区实现任何晶体管元件的阱掺杂剂浓度。

公开(公告)号：US20130313725A1

公开(公告)日：2013-11-28

申请号：US13953125

申请日：2013-07-29

申请人： GLOBAL FOUNDRIES Inc.

发明人： Ryoung-Han Kim

IPC分类号： H01L23/538

CPC分类号： H01L23/5384 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36′). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36′) making electrical contact with the first upper surface (61). A critical dimension (32, 37) between others (23) of lower conductors MN (22, 23) and the via conductor VN+1/N (36, 36′) is lengthened. Leakage current and electro-migration there-between are reduced.

摘要翻译： 多层互连结构通过提供一种衬底（40）形成，衬底（40）上具有第一电介质（50,27），用于支撑具有下导体MN（22,23），上导体MN + 1（ 34,35），电介质中间层（DIL）（68），并通过导体VN + 1 / N（36,36'）互连。 下导体MN（22,23）具有位于第一电介质（50,27）的第二上表面（56）下方的凹部中的第一上表面（61）。 DIL（68）形成在第一（61）和第二（56）表面上方。 通过DIL（68）从上导体MN + 1（34）的期望位置（122）蚀刻空腔（1263），露出第一表面（61）。 空腔（1263）填充有另外的电导体（80）以形成上导体MN + 1（34），并且连接通孔导体VN + 1 / N（36,36'）与第一上表面 （61）。 下导体MN（22,23）和通孔导体VN + 1 / N（36,36'）的其他（23）之间的临界尺寸（32,37）被延长。 泄漏电流和电迁移减少。

公开(公告)号：US20130130449A1

公开(公告)日：2013-05-23

申请号：US13718346

申请日：2012-12-18

申请人： GLOBAL FOUNDRIES Inc.

发明人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

摘要： Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.

摘要翻译： 基于嵌入式应变诱发半导体合金，可以通过基于高k介电材料与含金属盖层组合形成栅电极结构来增强P沟道晶体管的性能，以获得 栅电极结构的底切配置。 因此，应变诱导半导体合金可以基于最小厚度的侧壁间隔物形成，以便使应变诱导半导体材料更靠近沟道区的中心区域。

公开(公告)号：US09928335B2

公开(公告)日：2018-03-27

申请号：US14728100

申请日：2015-06-02

申请人： GLOBAL FOUNDRIES INC.

发明人： James M. Johnson ,  Sungjae Lee ,  Lan Luo ,  Scott K. Springer

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/80

摘要： Aspects of the present disclosure include a computer-implemented method for designing a temperature-compliant integrated circuit (IC). The method can include: calculating a thermal resistance of an IC layout, the IC layout having an area-dependent thermal conductance, a fin thermal conductance, and a gate thermal conductance each based on a device geometry of a plurality of transistors in the IC layout; calculating a self-heating temperature as directly proportional to the thermal resistance; comparing the self-heating temperature with a threshold temperature; in response to the self-heating temperature exceeding the threshold temperature, automatically modifying the device geometry of the IC layout to reduce at least one of the area term and the perimeter term, thereby reducing the self-heating temperature of the IC layout; and designing the temperature-compliant IC layout by repeating the calculating and automatically modifying steps until the self-heating temperature does not exceed the threshold temperature.

公开(公告)号：US20170200698A1

公开(公告)日：2017-07-13

申请号：US14994289

申请日：2016-01-13

申请人： Global Foundries Inc.

发明人： Richard S. Graf ,  Sebastian T. Ventrone

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L24/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/50 ,  H01L29/40 ,  H01L29/41 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/50 ,  H01L2224/73261 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06579 ,  H01L2924/15311

摘要： A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

公开(公告)号：US20160336399A1

公开(公告)日：2016-11-17

申请号：US14712388

申请日：2015-05-14

申请人： GLOBAL FOUNDRIES Inc.

发明人： Andre LABONTE ,  Ryan Ryoung-han KIM

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/78

摘要： There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length.

摘要翻译： 这里提出了用于门的栅极接触结构。 栅极接触结构可以包括第一接触层和第二接触层。 在一个实施例中，栅极接触层可以限定提供栅极接合的接触。 在一个实施例中，栅极接触层可以具有大于栅极长度的最小宽度。

公开(公告)号：US20160254345A1

公开(公告)日：2016-09-01

申请号：US14634255

申请日：2015-02-27

申请人： GLOBAL FOUNDRIES Inc.

发明人： Jagar SINGH ,  Scott BEASOR

IPC分类号： H01L49/02

CPC分类号： H01L28/75 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5329 ,  H01L27/016 ,  H01L28/20

摘要： A semiconductor structure includes a semiconductor substrate, semiconductor device(s) on the substrate, and metal resistor layer(s) above the semiconductor device(s), each metal resistor layer acting as a first plate for a MIM capacitor. The structure further includes a layer of insulator material above the first plate, and metal conductor layer(s) above the insulator layer, each metal conductor layer acting as a second plate for a MIM capacitor. Fabricating the MIM capacitor uses metal and insulator used in creating electrical connections to the semiconductor device(s), saving two masks typically used to fabricate a MIM capacitor.

摘要翻译： 半导体结构包括半导体衬底，衬底上的半导体器件和半导体器件之上的金属电阻器层，每个金属电阻层用作MIM电容器的第一板。 该结构还包括在第一板上方的绝缘体材料层和绝缘体层之上的金属导体层，每个金属导体层用作MIM电容器的第二板。 制造MIM电容器使用金属和绝缘体用于产生与半导体器件的电连接，从而节省了通常用于制造MIM电容器的两个掩模。