公开(公告)号：US20240194234A1

公开(公告)日：2024-06-13

申请号：US18443997

申请日：2024-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  H01L21/822

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US20240162333A1

公开(公告)日：2024-05-16

申请号：US18421398

申请日：2024-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66742 ,  H01L29/78696

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

公开(公告)号：US20240154016A1

公开(公告)日：2024-05-09

申请号：US18414753

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/401 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/0673

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US20240136428A1

公开(公告)日：2024-04-25

申请号：US18401833

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/78696 ,  H01L21/823468

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US11935937B2

公开(公告)日：2024-03-19

申请号：US17577169

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

公开(公告)号：US11935624B2

公开(公告)日：2024-03-19

申请号：US18302560

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  H01L21/822

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US20240071767A1

公开(公告)日：2024-02-29

申请号：US18150861

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Ju Chen ,  Chi On Chui ,  Tsung-Da Lin ,  Pei Ying Lai ,  Chia-Wei Hsu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/28158 ,  H01L21/0206 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31122 ,  H01L29/401 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/42392

Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

公开(公告)号：US11916132B2

公开(公告)日：2024-02-27

申请号：US17854599

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66742 ,  H01L29/78696

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

公开(公告)号：US20240015976A1

公开(公告)日：2024-01-11

申请号：US18152585

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chia-En Huang ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528

CPC classification number: H10B51/20 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L23/5283

Abstract: In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.

公开(公告)号：US11862468B2

公开(公告)日：2024-01-02

申请号：US17162270

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Lun Lin ,  Chia-Wei Hsu ,  Xiong-Fei Yu ,  Chi On Chui ,  Chih-Yu Hsu ,  Jian-Hao Chen

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3205 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3213

CPC classification number: H01L21/28185 ,  H01L21/28525 ,  H01L21/32055 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/32135

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.