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    METHOD FOR PERFORMING SWITCHING FUNCTION AND SWITCHING DEVICE
    15.
    发明公开
    METHOD FOR PERFORMING SWITCHING FUNCTION AND SWITCHING DEVICE 审中-公开

    公开(公告)号：US20240236019A9

    公开(公告)日：2024-07-11

    申请号：US18277316

    申请日：2021-10-01

    Applicant: MITSUBISHI ELECTRIC CORPORATION

    Inventor： ROMAIN ROLLET

    IPC: H04L49/253 ,  H04L45/00 ,  H04L47/6275 ,  H04L49/25

    CPC classification number: H04L49/254 ,  H04L45/66 ,  H04L47/6275 ,  H04L49/252

    Abstract: The present disclosure relates to a method for performing switching functions by a processing circuit of a switching device, the communication over the communication channel being organized according to successive first time slices and a second time slices, the processing circuit implementing a RTOS which in normal operation comprises a RTOS scheduler for scheduling a plurality of tasks having different priorities, said method comprising:



    applying, by the processing circuit, a first operating mode during each first time slice, in which normal operation of the RTOS is suspended and the processing circuit executes a single task which performs the switching functions;
    applying, by the processing circuit, a second operating mode in each second time slice, in which normal operation of the RTOS is resumed and switching functions are performed by a task which has not the highest priority of RTOS scheduler.

    System and method to manage data exchanges in a decentralized network
    16.
    发明授权
    System and method to manage data exchanges in a decentralized network 有权

    公开(公告)号：US12034807B1

    公开(公告)日：2024-07-09

    申请号：US18477652

    申请日：2023-09-29

    Applicant: Bank of America Corporation

    Inventor： Gowri Sundar Suriyanarayanan ,  Maneesh Kumar Sethia ,  Abhijit Behera ,  Shailendra Singh

    IPC: H04L67/1097 ,  H04L47/6275

    CPC classification number: H04L67/1097 ,  H04L47/6275

    Abstract: An apparatus comprises a memory communicatively coupled to a processor. The memory may be configured to store data exchange requests. The processor may be configured to determine that a data exchange request of the data exchange requests comprises a status indicating that the data exchange request is incomplete, generate a priority value for the data exchange request indicating a batch priority associated with the data exchange request, and assign a weight for the data exchange request indicating that the data exchange request is expected to be completed in one or more batch orders. Further, the processor is configured to generate a batch order comprising a position in a queue corresponding to the batch priority and complete the data exchange request in the decentralized network in accordance with the position in the batch order.

    METHOD AND A SYSTEM FOR NETWORK-ON-CHIP ARBITRATION
    19.
    发明公开
    METHOD AND A SYSTEM FOR NETWORK-ON-CHIP ARBITRATION 审中-公开

    公开(公告)号：US20240163223A1

    公开(公告)日：2024-05-16

    申请号：US18064988

    申请日：2022-12-13

    Applicant: SKYECHIP SDN BHD

    Inventor： YEONG TAT LIEW ,  YU YING ONG ,  SOON CHIEH LIM ,  WENG LI LEOW ,  CHEE HAK TEH

    IPC: H04L47/62 ,  H04L47/6275

    CPC classification number: H04L47/623 ,  H04L47/6225 ,  H04L47/6275

    Abstract: The present invention relates to a method (100) for network-on-chip arbitration. The method (100) comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight. A system (200) for network-on-chip arbitration is also disclosed herein.

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