公开(公告)号：US06320262B1

公开(公告)日：2001-11-20

申请号：US09205854

申请日：1998-12-04

Applicant: Akishige Murakami

Inventor： Akishige Murakami

IPC: H01L2348

CPC classification number: H01L23/53214 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05556 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14 ,  Y10S257/919 ,  Y10S257/92

Abstract: The present invention aims at improving the lifetime of the wiring connecting to the hole nearest to the bonding pad and thereby improving the reliability of the semiconductor device. The invention relates to such semiconductor device and method of manufacturing the semiconductor device. The semiconductor device includes a plurality of first metal layers connected to a bonding pad, and plurality of aluminum wirings respectively connected to the first metal layers. The plurality of aluminum wirings are connected to a single second metal layer and have a length equal to or short than Blech Length.

Abstract translation: 本发明旨在提高连接到最接近焊盘的孔的布线的寿命，从而提高半导体器件的可靠性。 本发明涉及这种半导体器件及其制造方法。 半导体器件包括连接到焊盘的多个第一金属层和分别连接到第一金属层的多个铝布线。 多个铝布线连接到单个第二金属层并且具有等于或短于Blech Length的长度。

公开(公告)号：US5610429A

公开(公告)日：1997-03-11

申请号：US517641

申请日：1995-08-22

Applicant: Harold S. Crafts

Inventor： Harold S. Crafts

IPC: H01L27/02 ,  H01L27/105 ,  H01L27/085

CPC classification number: H01L27/0203 ,  Y10S257/919

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.

Abstract translation: 本发明涉及将集成电路（IC）中的各个场效应晶体管（FET）互连的方法，以便提供更大的复合晶体管。 在一种方法中，各个FET对称地定位在质心上，质心本身对称地分布在IC上。 本发明允许将各个数字晶体管连接到较大的复合模拟晶体管中。

公开(公告)号：US5189595A

公开(公告)日：1993-02-23

申请号：US837727

申请日：1992-02-19

Applicant: James Dunkley

Inventor： James Dunkley

IPC: H01L27/04 ,  H01G13/00 ,  H01L21/82 ,  H01L21/822 ,  H01L27/08

CPC classification number: H01L27/0805 ,  H01G13/00 ,  Y10S257/919

Abstract: Improved, edge compensated capacitors and a method for making the same are presented. The present invention arranges individual cells of capacitors and uses passive dummy cells so as to achieve a ratio between the length of the exposed perimeters of the cells of the two capacitors that is equal to the desired capacitance ratio between the two capacitors. By doing so, the edge shrinkage effects on both cells are taken into account, and accurate capacitor ratios are maintained. In one embodiment of the invention the number of intersections between exposed edges of the cells of the two capacitors are also adjusted to conform to the capacitor ratio to achieve additional edge shrinkage compensation.

Abstract translation: 提出了改进的边缘补偿电容器及其制造方法。 本发明设置电容器的单个电池，并使用被动虚拟电池，以实现两个电容器的电池的暴露周长的长度与两个电容器之间的期望电容比相等的比率。 通过这样做，考虑了对两个电池的边缘收缩效应，并且保持精确的电容器比率。 在本发明的一个实施例中，两个电容器的单元的暴露边缘之间的交点数也被调整以符合电容器比率以实现额外的边缘收缩补偿。

公开(公告)号：US3802968A

公开(公告)日：1974-04-09

申请号：US87501169

申请日：1969-11-10

Applicant: IBM

Inventor： GHOSH H ,  WAJDA E

IPC: H01L21/00 ,  H01L21/74 ,  H01L27/00 ,  H01L29/08 ,  H01L7/00 ,  H01L19/00

CPC classification number: H01L29/0826 ,  H01L21/00 ,  H01L21/74 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/098 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S257/919

Abstract: A process for forming a self-isolated monolithic device by providing a substrate of a first conductivity type and forming an epitaxial layer of same conductivity type over the substrate. The epitaxial layer and the substrate are subjected to treatment so as to outdiffuse an impurity of opposite conductivity from the substrate and into the epitaxial layer so as to form a region which constitutes an element of the integrated circuit device and also defines an isolation PN junction with the epitaxial layer. Further, a pedestal transistor process forms a pedestal transistor for monolithic circuits by outdiffusing an impurity to form a subcollector region and outdiffusing another impurity having a higher diffusion rate to form the pedestal region. An extrinsic collector region defines an extrinsic junction with a lighter doped extrinsic base region so as to reduce overall base to collector capacitance.

公开(公告)号：US5677888A

公开(公告)日：1997-10-14

申请号：US473041

申请日：1995-06-06

Applicant: Sik K. Lui ,  Raymond M. Chu ,  David J. Pilling

Inventor： Sik K. Lui ,  Raymond M. Chu ,  David J. Pilling

IPC: G06F11/00 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C29/781 ,  G06F11/00 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785 ,  Y10S257/919

Abstract: An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.

Abstract translation: 反熔丝冗余电路对外部电路和用户具有透明度。 在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。 电路被布置成使得两个反熔丝可以被同时编程和读取。 如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。 此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。 结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

公开(公告)号：US5488249A

公开(公告)日：1996-01-30

申请号：US239166

申请日：1994-05-06

Applicant: Harold S. Crafts

Inventor： Harold S. Crafts

IPC: H03F3/45 ,  H01L27/02 ,  H01L27/088 ,  H01L27/105 ,  H01L27/085

CPC classification number: H01L27/0203 ,  H01L27/088 ,  Y10S257/919

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.

Abstract translation: 本发明涉及将集成电路（IC）中的各个场效应晶体管（FET）互连的方法，以便提供更大的复合晶体管。 在一种方法中，各个FET对称地定位在质心上，质心本身对称地分布在IC上。 本发明允许将各个数字晶体管连接到较大的复合模拟晶体管中。

公开(公告)号：US4928156A

公开(公告)日：1990-05-22

申请号：US319000

申请日：1989-03-06

Applicant: John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

Inventor： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/7836 ,  Y10S257/919

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

Abstract translation: 具有n型源极/漏极区域的金属氧化物半导体（MOS）晶体管在源/漏极中或附近也具有锗掺杂区域。 分级源极漏极（GSD），轻掺杂漏极（LDD）和双扩散漏极（DDD）中磷附近或位置处的锗的存在提供了漏极区的更好的轮廓，其结点深度低于磷获得的结点深度 或特别是磷和砷一起。 获得漏极结的良好分级，以避免热载流子不稳定或热载流子注入问题，同时连接浅源极结，这可以最大限度地减小横向掺杂剂扩散，并减小GSD和LDD中n +和n +区之间的距离。

公开(公告)号：US4864382A

公开(公告)日：1989-09-05

申请号：US148052

申请日：1988-01-25

Applicant: Masaaki Aoki ,  Kazuo Yano ,  Toshiaki Masuhara

Inventor： Masaaki Aoki ,  Kazuo Yano ,  Toshiaki Masuhara

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/66992 ,  H01L27/10805 ,  H01L29/1083 ,  H01L29/167 ,  Y10S257/919

Abstract: A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.

Abstract translation: 在半导体本体中形成MOS存储器，而在MOS存储器部分和半导体体之间的边界处设置阻挡半导体层，以便降低由α-粒子激发的不希望的载流子的影响。 阻挡半导体层被设计为允许在低温下操作存储器，同时减少由于α-粒子引起的软错误的发生。

公开(公告)号：US4803533A

公开(公告)日：1989-02-07

申请号：US913785

申请日：1986-09-30

Applicant: Mike F. Chang ,  Hamza Yilmaz ,  George L. Gauffreau ,  King Owyang

Inventor： Mike F. Chang ,  Hamza Yilmaz ,  George L. Gauffreau ,  King Owyang

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0878 ,  H01L21/2253 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66712 ,  H01L29/7802 ,  Y10S257/914 ,  Y10S257/919

Abstract: During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacent channel region. During subsequent high temperature processing the low diffusion coefficient drain-forming dopant remains concentrated near the top surface of the substrate while other well-forming dopants, including an adjacent channel-forming dopant, which have relatively higher diffusion coefficients, diffuse to deeper regions of the substrate. The slow-diffusing drain-forming dopant retards lateral widening of the channel by the faster-diffusing channel-forming dopant just below the substrate surface to at least the depth of the channel inversion layer formed under the channel surface during device turn on. Retardation of lateral channel growth just below the substrate surface results in an insulated gate device of reduced channel length and improved transconductance.In a preferred embodiment, the slow-diffusing drain-forming dopant is implanted on the substrate surface together with a fast-diffusing drain-forming dopant, and the latter is diffused to a pinch off depth below the substrate surface to counteract pinch off resistance between opposed segments of an adjacent shallow channel-forming well.

Abstract translation: 在制造绝缘栅极器件期间，沿着重叠待形成的垂直漏极区域和待形成的相邻沟道区域之间的边界的衬底表面注入具有相对较低扩散系数的漏极形成掺杂剂。 在随后的高温处理期间，低扩散系数漏极形成掺杂剂保留集中在衬底的顶表面附近，而具有相对较高扩散系数的其它阱形成掺杂剂（包括相邻沟道形成掺杂剂）扩散到 基质。 缓慢扩散的漏极形成掺杂剂通过在器件开启期间刚好在衬底表面正下方的较快扩散的沟道形成掺杂剂延迟至少在沟道表面下形成的沟道反转层的深度而延迟沟道的横向加宽。 在衬底表面正下方的横向通道生长的延迟导致具有减小的沟道长度和改进的跨导的绝缘栅极器件。 在优选实施例中，缓慢扩散的形成漏极的掺杂剂与快速扩散的形成漏极的掺杂剂一起注入到衬底表面上，并且后者扩散到衬底表面下方的夹断深度以抵消在衬底表面之下的夹断电阻 相邻浅沟道形成井的相对段。

公开(公告)号：US4017887A

公开(公告)日：1977-04-12

申请号：US535062

申请日：1974-12-20

Applicant: D. Eirug Davies ,  Sven A. Roosild ,  Russell P. Dolan, Jr.

Inventor： D. Eirug Davies ,  Sven A. Roosild ,  Russell P. Dolan, Jr.

IPC: H01L21/263 ,  H01L21/265 ,  H01L29/207 ,  H01L29/34 ,  H01L27/04 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L21/2654 ,  H01L21/263 ,  H01L29/207 ,  Y10S257/919

Abstract: The use of ion implantation to produce low concentrations of chromium, oxygen or iron in a gallium arsenide junction type semiconductor, utilizing the accompanying low resistivity to provide an improved device.

Abstract translation: 使用离子注入在砷化镓结型半导体中产生低浓度的铬，氧或铁，利用伴随的低电阻率提供改进的器件。