公开(公告)号：US12107163B2

公开(公告)日：2024-10-01

申请号：US17406395

申请日：2021-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsai-Jung Ho ,  Tze-Liang Lee

IPC: H01L21/265 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7847 ,  H01L29/04 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L21/823814 ,  H01L21/823821

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin, forming a gate spacer on opposing sides of the sacrificial gate structure, forming an amorphized region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface having a first roughness, forming a stressor layer over the amorphized region, wherein the formation of the stressor layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is less than the first roughness, and subjecting the amorphized region to an annealing process to recrystallize the amorphized region to a crystalline region, and the crystalline region comprising a dislocation.

公开(公告)号：US12107149B2

公开(公告)日：2024-10-01

申请号：US18302474

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US12107011B2

公开(公告)日：2024-10-01

申请号：US18360332

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Yuan Chen ,  Li-Zhen Yu ,  Huan-Chieh Su ,  Lo-Heng Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696 ,  H01L29/6681

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

公开(公告)号：US20240321959A1

公开(公告)日：2024-09-26

申请号：US18187706

申请日：2023-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Shogo Mochizuki ,  Kisik Choi ,  HUIMEI ZHOU ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/76843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An upper portion of a source/drain epitaxy adjacent to channel layers of a nanosheet stack on a substrate, a lower portion of the source/drain epitaxy below the upper portion of the source/drain epitaxy, a second width of the lower portion of the source/drain epitaxy is greater than a first width of the upper portion of the source/drain epitaxy, a dielectric fill layer below the nanosheet stack, and a dielectric encapsulation liner between the dielectric fill layer and the lower portion of the source/drain epitaxy. Forming an upper portion of a source/drain epitaxy adjacent to semiconductor channel layers of a nanosheet stack, and forming a lower portion of the source/drain epitaxy below the upper portion of the source/drain epitaxy, a second width of the lower portion of the source/drain epitaxy is greater than a first width of the upper portion of the source/drain epitaxy.

公开(公告)号：US20240321892A1

公开(公告)日：2024-09-26

申请号：US18125880

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Glenn Glass ,  Jessica Panella ,  Dan S. Lavric ,  Charles H. Wallace

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Techniques to form semiconductor devices having one or more epitaxial source or drain regions formed between dielectric walls that separate each adjacent pair of source or drain regions. In an example, a semiconductor device includes a semiconductor region extending in a first direction from a source or drain region. Dielectric walls extend in the first direction adjacent to opposite sides of the source or drain region. The first and second dielectric walls also extend in the first direction through a gate structure present over the semiconductor region. A dielectric liner exists between at least a portion of the first side of the source or drain region and the first dielectric wall and/or at least a portion of the second side of the source or drain region and the second dielectric wall. The dielectric walls may separate the source or drain region from other adjacent source or drain regions.

公开(公告)号：US20240321890A1

公开(公告)日：2024-09-26

申请号：US18673632

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Te-Hsin Chiu ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC: H01L27/092 ,  H01L21/764 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

公开(公告)号：US12101921B2

公开(公告)日：2024-09-24

申请号：US17871764

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H10B10/00 ,  G11C11/412 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20240313054A1

公开(公告)日：2024-09-19

申请号：US18183468

申请日：2023-03-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jianwei PENG ,  Hong Yu

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/6656 ,  H01L21/31144

Abstract: An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

公开(公告)号：US20240312844A1

公开(公告)日：2024-09-19

申请号：US18673432

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Wei Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/41791

Abstract: A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI. The metal compound feature extends continuously from the top surface of the NEPI to the top surface of the PEPI. The semiconductor structure further includes a contact feature disposed on the metal compound feature and a via structure disposed over the contact feature.

公开(公告)号：US12087776B2

公开(公告)日：2024-09-10

申请号：US17586089

申请日：2022-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lien Huang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7851

Abstract: The method for forming a semiconductor device includes forming gate spacers on a substrate; forming a gate structure on the substrate and laterally between the gate spacers; forming a protective cap over the gate structure and laterally between the gate spacers; forming source/drain structures over the substrate and on opposite sides of the gate structure; depositing a dielectric layer over the protective cap, the gate spacers, and the source/drain structures; performing an etching process on the dielectric layer to form an opening exposing one of the source/drain structures, the etching process further etching a first one of the gate spacers to expose the protective cap; selectively depositing a capping material on the exposed protective cap; forming a source/drain contact in the opening.