公开(公告)号：US10163835B2

公开(公告)日：2018-12-25

申请号：US15837403

申请日：2017-12-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Su-Chun Yang ,  Yi-Li Hsiao ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/78 ,  B23K1/00 ,  H01L25/065 ,  H01L25/00

摘要： A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.

公开(公告)号：US10034390B2

公开(公告)日：2018-07-24

申请号：US15004395

申请日：2016-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Li Hsiao ,  Su-Chun Yang ,  Chih-Hang Tung ,  Da-Yuan Shih ,  Chen-Hua Yu

IPC分类号： H01R43/00 ,  H05K3/42 ,  H01L23/00 ,  H05K3/40 ,  H01L23/498

摘要： A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.

公开(公告)号：US12002761B2

公开(公告)日：2024-06-04

申请号：US17884579

申请日：2022-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/373 ,  H01L25/065

CPC分类号： H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/3736 ,  H01L23/5386 ,  H01L25/0657

摘要： A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US09842817B2

公开(公告)日：2017-12-12

申请号：US14554354

申请日：2014-11-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Su-Chun Yang ,  Yi-Li Hsiao ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/78 ,  B23K1/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/11 ,  B23K1/0016 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/75252 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75843 ,  H01L2224/7598 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

摘要： A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.

公开(公告)号：US09475145B2

公开(公告)日：2016-10-25

申请号：US13826362

申请日：2013-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Su-Chun Yang ,  Chung-Jung Wu ,  Hsiao-Yun Chen ,  Yi-Li Hsiao ,  Chih-Hang Tung ,  Da-Yuan Shih ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  B23K1/00 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/262 ,  B23K2101/40 ,  B23K2103/08 ,  C22C13/00 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/81947 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3841

摘要： A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.

摘要翻译： 一种方法包括将焊料凸块加热到焊料凸块的熔化温度以上。 焊料凸块被拉伸以增加焊料凸块的高度。 焊料凸块被冷却以在电气装置中形成焊料凸块接头。

公开(公告)号：US20130221521A1

公开(公告)日：2013-08-29

申请号：US13826362

申请日：2013-03-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Su-Chun Yang ,  Chung-Jung Wu ,  Hsiao-Yun Chen ,  Yi-Li Hsiao ,  Chih-Hang Tung ,  Da-Yuan Shih ,  Chen-Hua Yu

IPC分类号： B23K1/00 ,  H01L23/498

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/262 ,  B23K2101/40 ,  B23K2103/08 ,  C22C13/00 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/81947 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3841

摘要： A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.

摘要翻译： 一种方法包括将焊料凸块加热到焊料凸块的熔化温度以上。 焊料凸块被拉伸以增加焊料凸块的高度。 焊料凸块被冷却以在电气装置中形成焊料凸块接头。

公开(公告)号：US11955378B2

公开(公告)日：2024-04-09

申请号：US17876556

申请日：2022-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Li Hsiao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/60

CPC分类号： H01L21/76828 ,  H01L21/50 ,  H01L2021/60127

摘要： A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

公开(公告)号：US20230369156A1

公开(公告)日：2023-11-16

申请号：US17744737

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Su-Chun Yang ,  Jih-Churng Twu ,  Jiung Wu ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC分类号： H01L23/31 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC分类号： H01L23/3192 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/80 ,  H01L24/08 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/293 ,  H01L23/291 ,  H01L24/48 ,  H01L2224/48228 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L23/49838 ,  H01L23/49822 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08148 ,  H01L23/3142

摘要： A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

公开(公告)号：US20230207473A1

公开(公告)日：2023-06-29

申请号：US18167879

申请日：2023-02-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC分类号： H01L23/538 ,  H01L23/373 ,  H01L25/065 ,  H01L21/768 ,  H01L21/50

CPC分类号： H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/3736 ,  H01L23/5386 ,  H01L25/0657

摘要： A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US11342302B2

公开(公告)日：2022-05-24

申请号：US16264957

申请日：2019-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Ying-Jui Huang ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Ching-Hua Hsieh ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Su-Chun Yang

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683

摘要： A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.