公开(公告)号：US20220157649A1

公开(公告)日：2022-05-19

申请号：US17649503

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US20220157648A1

公开(公告)日：2022-05-19

申请号：US17666368

申请日：2022-02-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chan-Syun David YANG ,  Li-Te LIN ,  Yu-Ming LIN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/67

Abstract: An equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. The semiconductor device includes an etch stop layer, a material layer, and a mask layer. The mask layer has openings to expose portions of the material layer. The etching device is configured to emit a plurality of directional charged particle beams to etch the exposed portions of the material layer for forming gaps in the material layer, in which the etching device has plural ion extraction apertures to emit the directional charged particle beams. A vertical distance between the semiconductor device and the ion extraction apertures is determined in accordance with a profile of each of the gap, each of the directional charged particle beams has two energy peaks at two angles, and the angles are determined in accordance with a profile of each of the gaps and the vertical distance.

公开(公告)号：US20220013532A1

公开(公告)日：2022-01-13

申请号：US16924903

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng YOUNG ,  Sai-Hooi YEONG ,  Chih-Yu CHANG ,  Han-Jong CHIA ,  Chenchen Jacob WANG ,  Yu-Ming LIN

IPC: H01L27/11556 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/06 ,  G11C16/08 ,  G11C16/24

Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.

公开(公告)号：US20200303549A1

公开(公告)日：2020-09-24

申请号：US16898659

申请日：2020-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

公开(公告)号：US20190139825A1

公开(公告)日：2019-05-09

申请号：US16222640

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wei-Hao WU ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.

公开(公告)号：US20190097147A1

公开(公告)日：2019-03-28

申请号：US16201742

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Yu-Ming LIN ,  Ken-Ichi GOTO ,  Jean-Pierre COLINGE ,  Zhiqiang Wu

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US20180350662A1

公开(公告)日：2018-12-06

申请号：US15609197

申请日：2017-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wai-Yi LIEN ,  Yu-Ming LIN

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/28

Abstract: A semiconductor device includes an active region in a semiconductor substrate. A gate electrode is disposed over and crossing the active region. The active region includes a channel region, a source region and a drain region. A bottom conductive feature is disposed on the active region. A helmet layer is disposed on the gate electrode. A contact etch stop layer is disposed on a portion of the helmet layer. A first contact plug is disposed on the bottom conductive feature and the remaining portion of the helmet layer. A hard mask is disposed on the gate electrode. An etching selectivity between the helmet layer and the hard mask is larger than approximately 10.

公开(公告)号：US20240234530A1

公开(公告)日：2024-07-11

申请号：US18330229

申请日：2023-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung TSAI ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Yu-Ting LIN ,  Ming-Te CHEN ,  Yi-Hsiu HUANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.

公开(公告)号：US20240021682A1

公开(公告)日：2024-01-18

申请号：US18353027

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/41725 ,  H01L29/66545 ,  H01L29/401 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/28556 ,  H01L27/0886 ,  H01L27/0924 ,  H01L21/32137

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20230343633A1

公开(公告)日：2023-10-26

申请号：US18344965

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/31144 ,  H01L27/0886

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.