公开(公告)号：US20200035809A1

公开(公告)日：2020-01-30

申请号：US16592955

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US09871100B2

公开(公告)日：2018-01-16

申请号：US14812864

申请日：2015-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin ,  Ying-Lang Wang ,  Wei-Ken Lin ,  Chuan-Pu Liu

IPC: H01L29/06 ,  H01L27/08 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

公开(公告)号：US11735430B2

公开(公告)日：2023-08-22

申请号：US17206740

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin Wang ,  Hung-Ju Chou ,  Jiun-Ming Kuo ,  Wei-Ken Lin ,  Chun Te Li

IPC: H01L21/3105 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L21/3105 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/31051 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853 ,  H01L21/31053 ,  H01L21/823842

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further incudes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

公开(公告)号：US11705327B2

公开(公告)日：2023-07-18

申请号：US17712561

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/36

CPC classification number: H01L21/0228 ,  H01L21/0214 ,  H01L21/02126 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/31111 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6656 ,  H01L21/266 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US11295948B2

公开(公告)日：2022-04-05

申请号：US17201691

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/36

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US20210057546A1

公开(公告)日：2021-02-25

申请号：US17090121

申请日：2020-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US10854713B2

公开(公告)日：2020-12-01

申请号：US15865072

申请日：2018-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin ,  Ying-Lang Wang ,  Wei-Ken Lin ,  Chuan-Pu Liu

IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/12 ,  H01L21/84

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

公开(公告)号：US10833170B2

公开(公告)日：2020-11-10

申请号：US16592955

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US10304677B2

公开(公告)日：2019-05-28

申请号：US15952895

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/36

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US20190131436A1

公开(公告)日：2019-05-02

申请号：US15884395

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-En Cheng ,  Chun-Te Li ,  Kai-Hsuan Lee ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234

Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.