公开(公告)号：US10705766B2

公开(公告)日：2020-07-07

申请号：US16225907

申请日：2018-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L29/06 ,  G06F3/06 ,  H01L29/792 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/06 ,  H01L27/11578 ,  B82Y10/00 ,  G11C13/02 ,  G11C14/00 ,  G11C15/04 ,  H01L27/11514 ,  H01L29/78

Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

公开(公告)号：US20180374845A1

公开(公告)日：2018-12-27

申请号：US15633016

申请日：2017-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L21/822 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.

公开(公告)号：US10164061B2

公开(公告)日：2018-12-25

申请号：US15196126

申请日：2016-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11524

Abstract: A method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized. The nanocrystal is sandwiched in between the gate and the silicon layer, and the gate oxide layer surrounds the nanocrystal.

公开(公告)号：US09660107B1

公开(公告)日：2017-05-23

申请号：US15253189

申请日：2016-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L29/06 ,  H01L29/792 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: G06F3/0679 ,  B82Y10/00 ,  G06F3/0688 ,  G11C13/025 ,  G11C14/0018 ,  G11C14/009 ,  G11C15/046 ,  H01L21/02491 ,  H01L27/0688 ,  H01L27/11514 ,  H01L27/11578 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/792

Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

公开(公告)号：US20200098749A1

公开(公告)日：2020-03-26

申请号：US16697943

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L21/822 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.

公开(公告)号：US20200051870A1

公开(公告)日：2020-02-13

申请号：US16599307

申请日：2019-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/16 ,  H01L29/78

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US10269572B2

公开(公告)日：2019-04-23

申请号：US15836448

申请日：2017-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/306 ,  H01L29/45 ,  H01L29/417

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US10134915B2

公开(公告)日：2018-11-20

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Chung-Cheng Wu ,  Carlos H. Diaz ,  Chih-Hao Wang ,  Ken-Ichi Goto ,  Ta-Pen Guo ,  Yee-Chia Yeo ,  Zhiqiang Wu ,  Yu-Ming Lin

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/8256 ,  H01L21/8238 ,  H01L29/78

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US10062779B2

公开(公告)日：2018-08-28

申请号：US14720721

申请日：2015-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of manufacturing a Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, and part of the upper layer is exposed from an isolation insulating layer. A gate structure is formed over part of the fin structure. An amorphous layer is formed over the gate structure and the fin structure not covered by the gate structure. A recrystallized layer is formed by partially recrystallizing the amorphous layer over the fin structure not covered by the gate structure. A remaining amorphous layer which is not recrystallized is removed. Source and drain electrode layers are formed over the recrystallized layer.

公开(公告)号：US20180166457A1

公开(公告)日：2018-06-14

申请号：US15890523

申请日：2018-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H Diaz

IPC: H01L27/11551 ,  H01L29/423 ,  H01L29/41 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/49

Abstract: Non-volatile memory devices and methods of fabricating thereof are disclosed herein. An exemplary non-volatile memory device includes a heterostructure disposed over a substrate. A gate structure traverses the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and a channel region is defined between the source region and the drain region. The non-volatile memory device further includes a nanocrystal floating gate disposed in the channel region of the heterostructure between a first nanowire and a second nanowire. The first nanowire and the second nanowire extend between the source region and the drain region.