公开(公告)号：US11342379B2

公开(公告)日：2022-05-24

申请号：US16408898

申请日：2019-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Yuan-Tai Tseng

IPC: H01L27/24 ,  H01L45/00 ,  G11C5/06 ,  G11C13/00

Abstract: Some embodiments relate to a memory device. The memory device includes a top electrode overlying a bottom electrode. A data storage layer overlies the bottom electrode. The bottom electrode cups an underside of the data storage layer. The top electrode overlies the data storage layer. A top surface of the bottom electrode is aligned with a top surface of the top electrode.

公开(公告)号：US20220123207A1

公开(公告)日：2022-04-21

申请号：US17074843

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Chang-Chih Huang ,  Yuan-Tai Tseng ,  Kuo-Chyuan Tzeng ,  Yihuei Zhu

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

公开(公告)号：US20210134668A1

公开(公告)日：2021-05-06

申请号：US17007260

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huang Huang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen

IPC: H01L21/768 ,  G11C5/06 ,  G11C11/16 ,  H01L21/3213

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.

公开(公告)号：US20170125434A1

公开(公告)日：2017-05-04

申请号：US15408994

申请日：2017-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/792 ,  H01L21/768 ,  H01L21/311 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

公开(公告)号：US09570457B2

公开(公告)日：2017-02-14

申请号：US14468410

申请日：2014-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract translation: 提供了具有非对称轮廓的硬掩模的分裂栅极闪存单元器件的半导体结构。 半导体结构的半导体衬底包括第一源极/漏极区域和第二源极/漏极区域。 半导体结构的控制栅极和存储栅极在第一和第二源极/漏极区之间的半导体衬底上间隔开。 半导体结构的电荷捕获电介质结构被布置在存储器栅极的相邻侧壁和控制栅极之间，并且布置在存储器栅极下方。 半导体结构的硬掩模布置在控制栅极上并且包括不对称轮廓。 不对称轮廓在远离记忆门的高度逐渐变细。 还提供了一种用于制造具有不对称轮廓的硬掩模的一对分裂栅极闪存单元器件的方法。

公开(公告)号：US09048316B2

公开(公告)日：2015-06-02

申请号：US14013653

申请日：2013-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  G11C16/16 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76805 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/34 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.

Abstract translation: 提供半导体器件结构的机构的实施例。 半导体器件结构包括衬底和设置在衬底上的字线单元。 半导体器件还包括设置在衬底上并与字线单元相邻并且在存储器栅极的侧壁上的间隔物的存储器栅极。 间隔物和字线单元位于存储器栅极的相对侧。 此外，存储器栅极的顶表面和存储器栅极的侧壁之间的角度在约75°至约90°的范围内。

公开(公告)号：US08853768B1

公开(公告)日：2014-10-07

申请号：US13798393

申请日：2013-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/792 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成具有包括高边和短边的不对称侧壁的多个栅极结构。 多个栅极结构中的相邻的栅极结构被一个高的侧边侧区域和短侧边区域隔开。 所述方法还包括在所述多个栅极结构上形成间隔层，以及在所述高侧边侧区域和所述短边侧短边区域的底表面上形成间隔层，在所述间隔层上方沉积氧化物层， 氧化物层，并且选择性地蚀刻位于高侧高侧区域中的氧化物层的侧壁部分。

公开(公告)号：US20210351348A1

公开(公告)日：2021-11-11

申请号：US16866704

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chern-Yow Hsu ,  Chung-Chiang Min ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L27/24

Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

公开(公告)号：US20210111333A1

公开(公告)日：2021-04-15

申请号：US16601723

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Chang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsung-Hsueh Yang ,  Yuan-Tai Tseng ,  Sheng-Huang Huang ,  Chia-Hua Lin

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

公开(公告)号：US10825825B2

公开(公告)日：2020-11-03

申请号：US16510043

申请日：2019-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/78 ,  H01L21/28 ,  H01L29/34 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521 ,  H01L23/528 ,  H01L29/49 ,  H01L21/768

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.