公开(公告)号：US11532785B2

公开(公告)日：2022-12-20

申请号：US17074843

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Chang-Chih Huang ,  Yuan-Tai Tseng ,  Kuo-Chyuan Tzeng ,  Yihuei Zhu

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

公开(公告)号：US20220336530A1

公开(公告)日：2022-10-20

申请号：US17809935

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tzu Lin ,  Kuo-Chyuan Tzeng ,  Kao-Chao Lin ,  Chang-Chih Huang

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

公开(公告)号：US20210295912A1

公开(公告)日：2021-09-23

申请号：US16821208

申请日：2020-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chih Huang ,  Jui-Yu Pan ,  Kuo-Chyuan Tzeng

IPC: G11C13/00 ,  H01L45/00

Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

公开(公告)号：US11211120B2

公开(公告)日：2021-12-28

申请号：US16821208

申请日：2020-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chih Huang ,  Jui-Yu Pan ,  Kuo-Chyuan Tzeng

IPC: G11C13/00 ,  H01L45/00 ,  G11C11/56

Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

公开(公告)号：US20220123207A1

公开(公告)日：2022-04-21

申请号：US17074843

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Chang-Chih Huang ,  Yuan-Tai Tseng ,  Kuo-Chyuan Tzeng ,  Yihuei Zhu

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.