公开(公告)号：US20160104713A1

公开(公告)日：2016-04-14

申请号：US14526711

申请日：2014-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Hsieh ,  Chi-Wei Ho ,  Kao-Chao Lin ,  Josh Lin ,  Nai-Chao Su ,  Shih-Jung Tu ,  Po-Kai Hsu ,  Shih-Ching Lee ,  Chen-Ming Huang

IPC: H01L27/115 ,  H01L29/06 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/11526 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.

Abstract translation: 闪存器件设置在半导体衬底上。 闪存器件包括以行和列排列的闪存单元。 各个闪存单元包括相应的存取晶体管和相应的浮置栅极晶体管。 各个存取晶体管具有相应的存取栅极，并且相应的浮置栅极晶体管具有布置在相应浮动栅极上的各自的控制栅极。 第一和第二字线彼此平行地延伸并对应于彼此相邻的第一和第二行。 第一字线耦合到沿着第一行的存取晶体管的存取门。 第二字线耦合到沿着第二行的存取晶体管的存取门。 第一和第二字线的最近边缘包括至少一个从第一和第二字线之一的侧壁向外侧向第二和第二字线另一侧向侧壁延伸的翼。

公开(公告)号：US20160358930A1

公开(公告)日：2016-12-08

申请号：US15237906

申请日：2016-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Hsieh ,  Chi-Wei Ho ,  Kao-Chao Lin ,  Josh Lin ,  Nai-Chao Su ,  Shih-Jung Tu ,  Po-Kai Hsu ,  Shih-Ching Lee ,  Chen-Ming Huang

IPC: H01L27/115

CPC classification number: H01L27/11526 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.

公开(公告)号：US09437603B2

公开(公告)日：2016-09-06

申请号：US14526711

申请日：2014-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Hsieh ,  Chi-Wei Ho ,  Kao-Chao Lin ,  Josh Lin ,  Nai-Chao Su ,  Shih-Jung Tu ,  Po-Kai Hsu ,  Shih-Ching Lee ,  Chen-Ming Huang

IPC: H01L29/788 ,  H01L27/115 ,  H01L23/528 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/11526 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.

Abstract translation: 闪存器件设置在半导体衬底上。 闪存器件包括以行和列排列的闪存单元。 各个闪存单元包括相应的存取晶体管和相应的浮置栅极晶体管。 各个存取晶体管具有相应的存取栅极，并且相应的浮置栅极晶体管具有布置在相应浮动栅极上的各自的控制栅极。 第一和第二字线彼此平行地延伸并对应于彼此相邻的第一和第二行。 第一字线耦合到沿着第一行的存取晶体管的存取门。 第二字线耦合到沿着第二行的存取晶体管的存取门。 第一和第二字线的最近边缘包括至少一个从第一和第二字线之一的侧壁向外侧向第二和第二字线另一侧向侧壁延伸的翼。

公开(公告)号：US20220336530A1

公开(公告)日：2022-10-20

申请号：US17809935

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tzu Lin ,  Kuo-Chyuan Tzeng ,  Kao-Chao Lin ,  Chang-Chih Huang

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

公开(公告)号：US09947678B2

公开(公告)日：2018-04-17

申请号：US15237906

申请日：2016-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Hsieh ,  Chi-Wei Ho ,  Kao-Chao Lin ,  Josh Lin ,  Nai-Chao Su ,  Shih-Jung Tu ,  Po-Kai Hsu ,  Shih-Ching Lee ,  Chen-Ming Huang

IPC: G11C11/34 ,  H01L27/11526 ,  H01L27/11521 ,  H01L23/528 ,  H01L29/06 ,  H01L27/02 ,  H01L27/11519

CPC classification number: H01L27/11526 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/0642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.