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    Bit line and word line connection for memory array
    2.
    发明授权
    Bit line and word line connection for memory array 有权

    公开(公告)号：US11211120B2

    公开(公告)日：2021-12-28

    申请号：US16821208

    申请日：2020-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chang-Chih Huang ,  Jui-Yu Pan ,  Kuo-Chyuan Tzeng

    IPC: G11C13/00 ,  H01L45/00 ,  G11C11/56

    Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

    SELF-ALIGNED DOUBLE PATTERNING PROCESS AND SEMICONDUCTOR STRUCTURE FORMED USING THEREOF
    3.
    发明申请
    SELF-ALIGNED DOUBLE PATTERNING PROCESS AND SEMICONDUCTOR STRUCTURE FORMED USING THEREOF 有权

    公开(公告)号：US20210035809A1

    公开(公告)日：2021-02-04

    申请号：US17075875

    申请日：2020-10-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Wen Wang ,  Kuo-Chyuan Tzeng

    IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311

    Abstract: A method for fabrication of a semiconductor structure according to some embodiments of the present disclosure comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island connecting a first mandrel strip and a second mandrel strip. A first spacer is formed along first and second sidewalls of the mandrel island, the first mandrel strip, and the second mandrel strip. The first mandrel is then removed, and the target layer is patterned with the first spacer remains over the target layer. The first mandrel strip and the second mandrel strip are misaligned from one another.

    SELF-ALIGNED DOUBLE PATTERNING (SADP) METHOD
    5.
    发明申请
    SELF-ALIGNED DOUBLE PATTERNING (SADP) METHOD 审中-公开

    公开(公告)号：US20200098580A1

    公开(公告)日：2020-03-26

    申请号：US16587390

    申请日：2019-09-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Yu Pan ,  Kuo-Chyuan Tzeng ,  Lee-Chuan Tseng ,  Ying-Hua Chen

    IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033

    Abstract: The present disclosure relates to integrated circuit device manufacturing processes. A self-aligned double patterning method is provided. In the method, a lithography process for line cut that determines the locations of line termini is performed after forming a spacer layer alongside the mandrel and prior to stripping the mandrel. The lithographic mask for the line cut is aligned to the mandrel and the spacer layer using a mark made of the mandrel material and the spacer material. Compared to the previous approach where the line cut process is performed after the mandrel removal, in the disclosed approach, the line termini mask is made of the mandrel material and the spacer material, and is more distinguishable compared to a mark made of just the spacer material. Thereby, the methods provide robust photo alignment signal for the line cut photolithography and precise positioning of the line termini mask.

    SELF-ALIGNED DOUBLE PATTERNING PROCESS AND SEMICONDUCTOR STRUCTURE FORMED USING THEREOF
    6.
    发明申请
    SELF-ALIGNED DOUBLE PATTERNING PROCESS AND SEMICONDUCTOR STRUCTURE FORMED USING THEREOF 审中-公开

    公开(公告)号：US20200058514A1

    公开(公告)日：2020-02-20

    申请号：US16239751

    申请日：2019-01-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Wen Wang ,  Kuo-Chyuan Tzeng

    IPC: H01L21/308 ,  H01L21/311 ,  H01L21/768

    Abstract: A method comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island and a first mandrel strip, the mandrel island comprises a first sidewall and a second sidewall perpendicular to the first sidewall, and the first mandrel strip extends from the first sidewall of the mandrel island. A first spacer is formed along the first and second sidewalls of the mandrel island and a sidewall of the first mandrel strip. The first mandrel is removed from the target layer. The target layer is patterned when the first spacer remains over the target layer.

    Self-aligned double patterning (SADP) method
    7.
    发明授权
    Self-aligned double patterning (SADP) method 有权

    公开(公告)号：US10483119B1

    公开(公告)日：2019-11-19

    申请号：US16161421

    申请日：2018-10-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Yu Pan ,  Kuo-Chyuan Tzeng ,  Lee-Chuan Tseng ,  Ying-Hua Chen

    IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033

    Abstract: The present disclosure relates to integrated circuit device manufacturing processes. A self-aligned double patterning method is provided. In the method, a lithography process for line cut that determines the locations of line termini is performed after forming a spacer layer alongside the mandrel and prior to stripping the mandrel. The lithographic mask for the line cut is aligned to the mandrel and the spacer layer using a mark made of the mandrel material and the spacer material. Compared to the previous approach where the line cut process is performed after the mandrel removal, in the disclosed approach, the line termini mask is made of the mandrel material and the spacer material, and is more distinguishable compared to a mark made of just the spacer material. Thereby, the methods provide robust photo alignment signal for the line cut photolithography and precise positioning of the line termini mask.

    BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY
    10.
    发明申请
    BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY 有权

    公开(公告)号：US20210295912A1

    公开(公告)日：2021-09-23

    申请号：US16821208

    申请日：2020-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chang-Chih Huang ,  Jui-Yu Pan ,  Kuo-Chyuan Tzeng

    IPC: G11C13/00 ,  H01L45/00

    Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

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