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    Neuromorphic device and neuromorphic system including the same
    12.
    发明授权
    Neuromorphic device and neuromorphic system including the same 有权

    公开(公告)号：US11362868B2

    公开(公告)日：2022-06-14

    申请号：US16911801

    申请日：2020-06-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu Seol ,  Hongrak Son ,  Geunyeong Yu ,  Pilsang Yoon ,  Jaehun Jang

    IPC: H04L27/04 ,  H04L1/00 ,  H04L27/06 ,  G06N3/063 ,  G06N3/04

    Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

    NEUROMORPHIC PACKAGE DEVICES AND NEUROMORPHIC COMPUTING SYSTEMS
    13.
    发明申请
    NEUROMORPHIC PACKAGE DEVICES AND NEUROMORPHIC COMPUTING SYSTEMS 有权

    公开(公告)号：US20210125048A1

    公开(公告)日：2021-04-29

    申请号：US16881963

    申请日：2020-05-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Pilsang Yoon ,  Junghyun Hong

    IPC: G06N3/063 ,  G06N3/04 ,  G11C13/00

    Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.

    Electronic device using homomorphic encryption and encrypted data processing method thereof
    15.
    发明授权
    Electronic device using homomorphic encryption and encrypted data processing method thereof 有权

    公开(公告)号：US12170719B2

    公开(公告)日：2024-12-17

    申请号：US18379384

    申请日：2023-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-Young Jung ,  Jiyoup Kim ,  Changkyu Seol ,  Pilsang Yoon ,  Jinsoo Lim ,  Myunghoon Choi

    IPC: H04L9/00 ,  G06F21/32 ,  H04L9/08 ,  G06F21/60

    Abstract: An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.

    Neuromorphic package devices and neuromorphic computing systems
    17.
    发明授权
    Neuromorphic package devices and neuromorphic computing systems 有权

    公开(公告)号：US11620505B2

    公开(公告)日：2023-04-04

    申请号：US16881963

    申请日：2020-05-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Pilsang Yoon ,  Junghyun Hong

    IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C13/00

    Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.

    Storage device with artificial intelligence and storage system including the same
    18.
    发明授权
    Storage device with artificial intelligence and storage system including the same 有权

    公开(公告)号：US11468306B2

    公开(公告)日：2022-10-11

    申请号：US16906209

    申请日：2020-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Hyejeong So ,  Hwaseok Oh ,  Pilsang Yoon ,  Jinsoo Lim

    IPC: G06N3/063 ,  G06F15/80 ,  G06F7/544 ,  G06N3/08

    Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.

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