公开(公告)号：US11681553B2

公开(公告)日：2023-06-20

申请号：US16562623

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanmin Cho ,  Suengchul Ryu ,  Junghyun Hong

IPC: G06F12/02 ,  G06F9/50 ,  G06F13/16 ,  G06N3/06

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F12/0207 ,  G06F13/1673 ,  G06N3/06 ,  G06F2212/657 ,  G06F2212/7201

Abstract: A storage device includes an accelerator including a first processor, and a storage controller that uses a buffer memory as a working memory and includes a second processor different in type from the first processor. The second processor is configured to establish a first communication path between the first processor and the buffer memory responsive to a request of the first processor, and the first processor is configured to access the buffer memory through the first communication path.

公开(公告)号：US11620505B2

公开(公告)日：2023-04-04

申请号：US16881963

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Pilsang Yoon ,  Junghyun Hong

IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C13/00

Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.

公开(公告)号：US20210365193A1

公开(公告)日：2021-11-25

申请号：US17181579

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Hong ,  Youngjin Cho ,  Younggeon Yoo ,  Chanho Yoon ,  Hyeokjun Choe

IPC: G06F3/06 ,  G06F9/48

Abstract: A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

公开(公告)号：US11675506B2

公开(公告)日：2023-06-13

申请号：US17181579

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Hong ,  Youngjin Cho ,  Younggeon Yoo ,  Chanho Yoon ,  Hyeokjun Choe

IPC: G06F3/06 ,  G06F9/48

CPC classification number: G06F3/0631 ,  G06F3/0605 ,  G06F3/067 ,  G06F3/0659 ,  G06F9/4881

Abstract: A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

公开(公告)号：US20210125048A1

公开(公告)日：2021-04-29

申请号：US16881963

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Pilsang Yoon ,  Junghyun Hong

IPC: G06N3/063 ,  G06N3/04 ,  G11C13/00

Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.