公开(公告)号：US20240053917A1

公开(公告)日：2024-02-15

申请号：US18492762

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US20230384848A1

公开(公告)日：2023-11-30

申请号：US18305474

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Young JI ,  Younggeon Yoo ,  Brianmyungjune Jung ,  Sung Chul Hur

IPC: G06F1/26 ,  G06F1/30

CPC classification number: G06F1/263 ,  G06F1/305

Abstract: Disclosed is a storage device including a non-volatile memory that inputs or outputs data at a request of a host system, a volatile memory that temporarily stores data input to or output from the non-volatile memory, an internal spare power source that supplies power to a part of the volatile memory in response to main power supplied from the host system dropping to a first amount or less, and a storage controller that controls the non-volatile memory and the volatile memory. The storage controller is configured to divide the volatile memory into area-received-duplication-power, and at least one area-received-spare-power, in response to the main power dropping to the first amount or less, to redundantly supply spare power to the area-received-duplication-power from an external spare power source and the internal spare power source, and to supply the spare power to the at least one area-received-spare-power from the external spare power source.

公开(公告)号：US11586543B2

公开(公告)日：2023-02-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/00 ,  G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US12007884B2

公开(公告)日：2024-06-11

申请号：US17895260

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Shin ,  Jeongho Lee ,  Younggeon Yoo ,  Hyeokjun Choe

IPC: G06F12/02 ,  G06F12/14 ,  H04L9/08

CPC classification number: G06F12/02 ,  G06F12/14 ,  H04L9/0825

Abstract: In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.

公开(公告)号：US11983115B2

公开(公告)日：2024-05-14

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US20220121574A1

公开(公告)日：2022-04-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US12248700B2

公开(公告)日：2025-03-11

申请号：US17852022

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Jeongho Lee ,  Younggeon Yoo ,  Wonseb Jeong

IPC: G06F3/06

Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

公开(公告)号：US11822813B2

公开(公告)日：2023-11-21

申请号：US17680773

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US11762558B2

公开(公告)日：2023-09-19

申请号：US16533883

申请日：2019-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggeon Yoo ,  Changkyu Seol ,  Hyeonwu Kim ,  Hyeongseok Song

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0614 ,  G06F3/0629 ,  G06F3/0688

Abstract: A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

公开(公告)号：US11675506B2

公开(公告)日：2023-06-13

申请号：US17181579

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Hong ,  Youngjin Cho ,  Younggeon Yoo ,  Chanho Yoon ,  Hyeokjun Choe

IPC: G06F3/06 ,  G06F9/48

CPC classification number: G06F3/0631 ,  G06F3/0605 ,  G06F3/067 ,  G06F3/0659 ,  G06F9/4881

Abstract: A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.