公开(公告)号：US12079080B2

公开(公告)日：2024-09-03

申请号：US18335375

申请日：2023-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Heehyun Nam ,  Jeongho Lee ,  Younho Jeon

IPC: H03M13/15 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US11962675B2

公开(公告)日：2024-04-16

申请号：US18299972

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younho Jeon ,  Hyeokjun Choe ,  Jeongho Lee

IPC: H04L69/22 ,  H04L69/04 ,  H04L69/08

CPC classification number: H04L69/22 ,  H04L69/04 ,  H04L69/08

Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

公开(公告)号：US11586543B2

公开(公告)日：2023-02-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/00 ,  G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US20220147470A1

公开(公告)日：2022-05-12

申请号：US17466726

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Younho Jeon ,  Daehui Kim ,  Heehyun Nam

IPC: G06F13/16 ,  G06F13/40

Abstract: A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.

公开(公告)号：US11226823B2

公开(公告)日：2022-01-18

申请号：US16879120

申请日：2020-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younho Jeon ,  Youngjin Cho ,  Hee Hyun Nam ,  Hyo-Deok Shin

IPC: G06F9/30 ,  G06F1/12 ,  G06K9/62 ,  G06F12/02 ,  G06F9/54 ,  G06F1/08

Abstract: A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.

公开(公告)号：US11983115B2

公开(公告)日：2024-05-14

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US11720442B2

公开(公告)日：2023-08-08

申请号：US17510898

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Heehyun Nam ,  Jeongho Lee ,  Younho Jeon

IPC: H03M13/15 ,  G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US20220121574A1

公开(公告)日：2022-04-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US12056066B2

公开(公告)日：2024-08-06

申请号：US17466726

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Younho Jeon ,  Daehui Kim ,  Heehyun Nam

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/4022

Abstract: A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.

公开(公告)号：US11899970B2

公开(公告)日：2024-02-13

申请号：US17742184

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hee Hyun Nam ,  Younggeon Yoo ,  Jeongho Lee ,  Younho Jeon ,  Ipoom Jeong ,  Chanho Yoon

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0611 ,  G06F3/0622 ,  G06F3/0683

Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.