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公开(公告)号：US12079080B2
公开(公告)日：2024-09-03
申请号：US18335375
申请日：2023-06-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeokjun Choe , Heehyun Nam , Jeongho Lee , Younho Jeon
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F11/0772
Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.
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公开(公告)号：US12248700B2
公开(公告)日：2025-03-11
申请号：US17852022
申请日：2022-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeokjun Choe , Jeongho Lee , Younggeon Yoo , Wonseb Jeong
IPC: G06F3/06
Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.
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公开(公告)号：US11675506B2
公开(公告)日：2023-06-13
申请号：US17181579
申请日：2021-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junghyun Hong , Youngjin Cho , Younggeon Yoo , Chanho Yoon , Hyeokjun Choe
CPC classification number: G06F3/0631 , G06F3/0605 , G06F3/067 , G06F3/0659 , G06F9/4881
Abstract: A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.
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公开(公告)号：US20230185717A1
公开(公告)日：2023-06-15
申请号：US18166244
申请日：2023-02-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho LEE , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/0817 , G06F3/06 , G06F12/0862
CPC classification number: G06F12/0828 , G06F3/0622 , G06F3/0655 , G06F3/0679 , G06F12/0862 , G06F2212/602 , G06F2212/621
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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公开(公告)号：US11659070B2
公开(公告)日：2023-05-23
申请号：US17466742
申请日：2021-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Younho Jeon , Hyeokjun Choe , Jeongho Lee
Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.
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Patent Agency Ranking
公开(公告)号：US20210365193A1
公开(公告)日：2021-11-25
申请号：US17181579
申请日：2021-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junghyun Hong , Youngjin Cho , Younggeon Yoo , Chanho Yoon , Hyeokjun Choe
Abstract: A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.
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公开(公告)号：US12007884B2
公开(公告)日：2024-06-11
申请号：US17895260
申请日：2022-08-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeho Shin , Jeongho Lee , Younggeon Yoo , Hyeokjun Choe
CPC classification number: G06F12/02 , G06F12/14 , H04L9/0825
Abstract: In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.
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公开(公告)号：US11983115B2
公开(公告)日：2024-05-14
申请号：US18166244
申请日：2023-02-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/0817 , G06F3/06 , G06F12/0862
CPC classification number: G06F12/0828 , G06F3/0622 , G06F3/0655 , G06F3/0679 , G06F12/0862 , G06F2212/602 , G06F2212/621
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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公开(公告)号：US11720442B2
公开(公告)日：2023-08-08
申请号：US17510898
申请日：2021-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeokjun Choe , Heehyun Nam , Jeongho Lee , Younho Jeon
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F11/0772
Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.
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公开(公告)号：US20220121574A1
公开(公告)日：2022-04-21
申请号：US17380805
申请日：2021-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho LEE , Heehyun Nam , Jaeho Shin , Hyodeok Shin , Younggeon Yoo , Younho Jeon , Wonseb Jeong , Ipoom Jeong , Hyeokjun Choe
IPC: G06F12/0817 , G06F3/06 , G06F12/0862
Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
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