公开(公告)号：US12141480B2

公开(公告)日：2024-11-12

申请号：US18501412

申请日：2023-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongik Jeon ,  Kyungbo Yang ,  Seokwon Ahn ,  Hyeonwu Kim

IPC: G06F3/06

Abstract: A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.

公开(公告)号：US11544006B2

公开(公告)日：2023-01-03

申请号：US17032654

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongik Jeon ,  Kyungbo Yang ,  Seokwon Ahn ,  Hyeonwu Kim

IPC: G06F3/06

Abstract: A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.

公开(公告)号：US11762558B2

公开(公告)日：2023-09-19

申请号：US16533883

申请日：2019-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggeon Yoo ,  Changkyu Seol ,  Hyeonwu Kim ,  Hyeongseok Song

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0614 ,  G06F3/0629 ,  G06F3/0688

Abstract: A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

公开(公告)号：US11016904B2

公开(公告)日：2021-05-25

申请号：US16543531

申请日：2019-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongwon Cho ,  Hyeonwu Kim ,  Seok-Won Ahn

IPC: G06F12/00 ,  G06F12/1009

Abstract: A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.

公开(公告)号：US12216935B2

公开(公告)日：2025-02-04

申请号：US17067698

申请日：2020-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjoon Park ,  Youngho Gong ,  Hyeonwu Kim ,  Seokwon Ahn

IPC: G06F3/06

Abstract: A method of operating a storage device that includes a nonvolatile memory device and a controller that controls an operation of the nonvolatile memory device includes issuing, by the controller, a first command to the nonvolatile memory device, reading, by the nonvolatile memory device, first data from a memory cell array into a page buffer of the nonvolatile memory device, in response to the first command, issuing, by the controller, a second command to the nonvolatile memory device, and outputting, by the nonvolatile memory device to the controller, in response to the second command, status information indicating whether a read operation according to the first command has been completed and second data obtained from the page buffer of the nonvolatile memory device.

公开(公告)号：US12189536B2

公开(公告)日：2025-01-07

申请号：US18135894

申请日：2023-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbo Yang ,  Hyeonwu Kim ,  Dongik Jeon ,  Soonsuk Hwang

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

Abstract: A memory controller receives a write request and write data from a host, stores first entry information including a write buffer pointer indicating a location where the write data is temporarily stored in a write buffer and a first logical address corresponding to the write request in an entry buffer, stores an entry index generated based on the first entry information in a first storage space corresponding to the first logical address in a logical-to-physical (L2P) mapping information storage circuit, and updates the entry index stored in the first storage space to a physical address newly mapped to the first logical address as the write data is programmed in a memory device.

公开(公告)号：US11842082B2

公开(公告)日：2023-12-12

申请号：US18148534

申请日：2022-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongik Jeon ,  Kyungbo Yang ,  Seokwon Ahn ,  Hyeonwu Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.

公开(公告)号：US11119692B2

公开(公告)日：2021-09-14

申请号：US16510029

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonwu Kim ,  Daekyoung Kim ,  Seok-Won Ahn ,  Chanho Yoon

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

公开(公告)号：US20200150893A1

公开(公告)日：2020-05-14

申请号：US16510029

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonwu Kim ,  Daekyoung Kim ,  Seok-Won Ahn ,  Chanho Yoon

IPC: G06F3/06 ,  G11C16/32

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.