公开(公告)号：US10325898B2

公开(公告)日：2019-06-18

申请号：US15635615

申请日：2017-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sharma Deepak ,  Rajeev Ranjan ,  Kuchanuri Subhash ,  Chulhong Park ,  Jaeseok Yang ,  Kwanyoung Chun

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

公开(公告)号：US09929180B2

公开(公告)日：2018-03-27

申请号：US15496015

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L27/118 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/11807 ,  H01L23/535 ,  H01L23/5384 ,  H01L27/0207 ,  H01L29/0649 ,  H01L2924/0002 ,  H03K19/1736 ,  H01L2924/00

Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

公开(公告)号：US09324715B2

公开(公告)日：2016-04-26

申请号：US14504075

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上，第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极，并且连接线设置在连接触头上以与连接触头交叉，并将第一栅电极连接到第四栅电极。

公开(公告)号：US20240194521A1

公开(公告)日：2024-06-13

申请号：US18533635

申请日：2023-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisoo PARK ,  Junghan Lee ,  Kwanyoung Chun

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7684 ,  H01L21/76877

Abstract: A method of forming a pattern of a semiconductor device, the method comprising forming an insulating film on a substrate having a first region and a second region, sequentially forming a lower mask layer and an upper mask layer on the insulating film, forming a line-shaped hard mask pattern having a plurality of narrow openings having the same width in the first region and the second region, respectively, on the upper mask layer, forming line-shaped spacers on sidewalls of the opening of the line-shaped hard mask pattern, forming a composite mask pattern composed of the spacer and a pattern having a first width among the line-shaped hard mask pattern by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width.

公开(公告)号：US20230378027A1

公开(公告)日：2023-11-23

申请号：US18113133

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhyeong CHOI ,  Jiwook Kwon ,  Byungju Kang ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L23/48 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L23/5226

Abstract: A semiconductor device includes: a semiconductor substrate having power arrangement regions; a first interconnection structure disposed on the semiconductor substrate and including first interconnection patterns and power lines; a second interconnection structure disposed on the semiconductor substrate and including second interconnection patterns; and through-electrodes passing through each of the power arrangement regions and contacting the power lines, wherein the first interconnection patterns include first interconnection lines, wherein the power lines are disposed on a same height level as a first interconnection line, among the first interconnection lines, and are parallel to each other, wherein the power arrangement regions are parallel to each other, and wherein intersection regions, in which the power arrangement regions and the power lines intersect, include a plurality of first active intersection regions, one dummy intersection region, and a plurality of second active intersection regions, sequentially arranged.

公开(公告)号：US11804480B2

公开(公告)日：2023-10-31

申请号：US17527432

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae Park ,  Byungju Kang ,  Yoonjeong Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/786 ,  H01L23/528 ,  B82Y10/00

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

公开(公告)号：US11688740B2

公开(公告)日：2023-06-27

申请号：US17740900

申请日：2022-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/02 ,  H10B10/00

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US11522071B2

公开(公告)日：2022-12-06

申请号：US16730172

申请日：2019-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyung Kim ,  Kwanyoung Chun ,  Yoonjin Kim

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02

Abstract: Disclosed is a semiconductor device comprising an active region that protrudes upwardly from a substrate, a plurality of channel patterns that are spaced apart from each other in a first direction on the active region, and a gate electrode that extends in the first direction on the active region and covers the plurality of channel patterns. Each of the plurality of channel patterns includes a plurality of semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the active region. The gate electrode covers the top surface of the active region between the plurality of channel patterns.

公开(公告)号：US10297687B2

公开(公告)日：2019-05-21

申请号：US15821116

申请日：2017-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.

公开(公告)号：US20180151728A1

公开(公告)日：2018-05-31

申请号：US15821116

申请日：2017-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.