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    Stacked integrated circuit devices
    11.
    发明授权
    Stacked integrated circuit devices 有权

    公开(公告)号：US12002738B2

    公开(公告)日：2024-06-04

    申请号：US18327291

    申请日：2023-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do ,  Seungyoung Lee

    IPC: H01L23/48 ,  H01L27/02 ,  H01L27/088

    CPC classification number: H01L23/481 ,  H01L27/0207 ,  H01L27/088

    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

    Stacked integrated circuit devices including a routing wire
    12.
    发明授权
    Stacked integrated circuit devices including a routing wire 有权

    公开(公告)号：US11742287B2

    公开(公告)日：2023-08-29

    申请号：US17518627

    申请日：2021-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do

    IPC: H01L23/528 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L23/528 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

    Abstract: Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.

    Stacked integrated circuit devices
    14.
    发明授权
    Stacked integrated circuit devices 有权

    公开(公告)号：US11222831B2

    公开(公告)日：2022-01-11

    申请号：US16947241

    申请日：2020-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do ,  Seungyoung Lee

    IPC: H01L27/02 ,  H01L23/48 ,  H01L27/088

    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

    Stacked integrated circuit devices including a routing wire
    15.
    发明授权
    Stacked integrated circuit devices including a routing wire 有权

    公开(公告)号：US11195794B2

    公开(公告)日：2021-12-07

    申请号：US16947693

    申请日：2020-08-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do

    IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    Abstract: Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.

    Vertical field effect transistor with self-aligned contact structure and layout
    19.
    发明授权
    Vertical field effect transistor with self-aligned contact structure and layout 有权

    公开(公告)号：US11257913B2

    公开(公告)日：2022-02-22

    申请号：US16883308

    申请日：2020-05-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hwi Chan Jun ,  Jung Ho Do

    IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

    Abstract: Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region.

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