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公开(公告)号：US11699636B2
公开(公告)日：2023-07-11
申请号：US17540303
申请日：2021-12-02
发明人： Jung Ho Do , Seungyoung Lee
IPC分类号： H01L27/02 , H01L23/48 , H01L27/088
CPC分类号： H01L23/481 , H01L27/0207 , H01L27/088
摘要： Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
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公开(公告)号：US11189692B2
公开(公告)日：2021-11-30
申请号：US16711582
申请日：2019-12-12
发明人： Jung Ho Do , Rwik Sengupta
摘要： A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.
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3.发明申请公开(公告)号：US20200035829A1
公开(公告)日：2020-01-30
申请号：US16406305
申请日：2019-05-08
发明人： Jung Ho Do
IPC分类号： H01L29/78 , H01L27/088 , H01L29/423 , H03K3/3562
摘要： Integrated circuit devices are provided. The devices may include a substrate including a first region, a second region and a boundary region between the first and second regions. The first and second regions may be spaced apart from each other in a first horizontal direction. The devices may also include a first latch on the first region, a second latch on the second region, and a conductive layer extending in the first horizontal direction and crossing over the boundary region. The first latch may include a first vertical field effect transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The first and seventh VFETs may be arranged along the first horizontal direction. Portions of the conductive layer may include gate electrodes of the first and seventh VFETs, respectively.
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公开(公告)号：US12068325B2
公开(公告)日：2024-08-20
申请号：US18155386
申请日：2023-01-17
发明人： Jung Ho Do
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , H01L2027/11831 , H01L2027/11851 , H01L2027/11875 , H01L2027/11881
摘要： A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.
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公开(公告)号：US11581338B2
公开(公告)日：2023-02-14
申请号：US16941042
申请日：2020-07-28
发明人： Jung Ho Do
IPC分类号： H01L27/118
摘要： A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.
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公开(公告)号：US11056489B2
公开(公告)日：2021-07-06
申请号：US16434245
申请日：2019-06-07
发明人： Jung Ho Do
IPC分类号： H01L29/66 , H01L27/092 , H01L23/522 , H01L27/02
摘要： Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) having a first conductivity type, and a second VFET having a second conductivity type. The first VFET may include a first top source/drain region, a first channel region, and a first bottom source/drain region. The second VFET may include a second top source/drain region, a second channel region, and a second bottom source/drain region. The standard cells may also include a conductive line that is electrically connected to the first top source/drain region or the first bottom source/drain region and is electrically connected to the second bottom source/drain region. The standard cell may be configured to output an output signal thereof through the conductive line.
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公开(公告)号：US12046635B2
公开(公告)日：2024-07-23
申请号：US17510753
申请日：2021-10-26
发明人： Jung Ho Do , Rwik Sengupta
CPC分类号： H01L29/0696 , H01L29/0847 , H01L29/7827
摘要： A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.
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公开(公告)号：US11468221B2
公开(公告)日：2022-10-11
申请号：US16741209
申请日：2020-01-13
发明人： Jung Ho Do , Seung Hyun Song
IPC分类号： G06F30/392 , H01L27/02 , H01L23/528 , H01L29/78 , H01L27/092 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/08 , H01L29/417 , H01L29/66 , H01L27/11556
摘要： A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.
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公开(公告)号：US20220189944A1
公开(公告)日：2022-06-16
申请号：US17373510
申请日：2021-07-12
发明人： Jung Ho Do , Sanghoon Baek
IPC分类号： H01L27/02 , H01L27/092 , H01L23/528 , H01L29/417 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/786 , G06F30/392
摘要： A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.
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公开(公告)号：US12002738B2
公开(公告)日：2024-06-04
申请号：US18327291
申请日：2023-06-01
发明人： Jung Ho Do , Seungyoung Lee
IPC分类号： H01L23/48 , H01L27/02 , H01L27/088
CPC分类号： H01L23/481 , H01L27/0207 , H01L27/088
摘要： Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
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