-
公开(公告)号:US11810920B2
公开(公告)日:2023-11-07
申请号:US17027211
申请日:2020-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Su Yu , Jae-Ho Park , Sanghoon Baek , Hyeon Gyu You , Seung Young Lee , Seung Man Lim
IPC: H01L27/02 , H01L27/118
CPC classification number: H01L27/11807 , H01L27/0207 , H01L2027/11861 , H01L2027/11866 , H01L2027/11885
Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.
-
公开(公告)号:US11973081B2
公开(公告)日:2024-04-30
申请号:US17561887
申请日:2021-12-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeon Gyu You , In Gyum Kim , Gi Young Yang , Ji Su Yu , Jin Young Lim , Hak Chul Jung
IPC: H01L27/118 , H01L27/02
CPC classification number: H01L27/11807 , H01L27/0207 , H01L2027/11812 , H01L2027/1182 , H01L2027/11866 , H01L2027/11875 , H01L2027/11881 , H01L2027/11887
Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.
-
3.
公开(公告)号:US11488948B2
公开(公告)日:2022-11-01
申请号:US17109912
申请日:2020-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeon Gyu You , Ji Su Yu , Jae-Ho Park
IPC: H01L27/02 , H01L27/092 , H01L23/528 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786 , H01L29/78 , G06F30/392 , G06F30/394
Abstract: A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.
-
4.
公开(公告)号:US11355604B2
公开(公告)日:2022-06-07
申请号:US16857288
申请日:2020-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Su Yu , Hyeon Gyu You , Seung Man Lim
IPC: H01L29/417 , H01L27/088 , H01L29/40 , H01L29/78 , H01L23/522 , G06F30/392 , G06F30/3953 , H01L29/423 , H01L29/66 , H01L23/528 , G06F119/06
Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.
-
5.
公开(公告)号:US20210305232A1
公开(公告)日:2021-09-30
申请号:US17109912
申请日:2020-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeon Gyu You , Ji Su Yu , Jae-Ho Park
IPC: H01L27/02 , H01L27/092 , H01L23/528 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786 , H01L29/78 , G06F30/392 , G06F30/394
Abstract: A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.
-
6.
公开(公告)号:US11916120B2
公开(公告)日:2024-02-27
申请号:US17740829
申请日:2022-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Su Yu , Hyeon Gyu You , Seung Man Lim
IPC: H01L29/417 , H01L27/088 , H01L29/40 , H01L29/78 , H01L23/522 , G06F30/392 , G06F30/3953 , H01L29/423 , H01L29/66 , H01L23/528 , G06F119/06
CPC classification number: H01L29/41791 , G06F30/392 , G06F30/3953 , H01L23/528 , H01L23/5226 , H01L27/0886 , H01L29/401 , H01L29/42372 , H01L29/66795 , H01L29/785 , G06F2119/06
Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.
-
公开(公告)号:US20230335492A1
公开(公告)日:2023-10-19
申请号:US18153550
申请日:2023-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Ho Do , Ji Su Yu , Jae Ha Lee
IPC: H01L23/528 , H01L23/48 , H01L27/092 , H01L29/417 , H01L29/06 , H01L29/423 , H01L29/775
CPC classification number: H01L23/5286 , H01L23/481 , H01L27/0924 , H01L27/0928 , H01L29/41791 , H01L29/0673 , H01L29/42392 , H01L29/41733 , H01L29/775
Abstract: According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source/drain region having the second conductivity type, on the first well; a first source/drain contact extending in a second direction and electrically connected to the first power rail, on the first source/drain region, a first connection wiring electrically connected to the first source/drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.
-
公开(公告)号:US11764201B2
公开(公告)日:2023-09-19
申请号:US17158109
申请日:2021-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Su Yu , Jae-Woo Seo , Sanghoon Baek , Hyeon Gyu You
IPC: H01L27/02 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , G06F30/392
CPC classification number: H01L27/0207 , G06F30/392 , H01L23/5286 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78618 , H01L29/78696
Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.
-
公开(公告)号:US11244961B2
公开(公告)日:2022-02-08
申请号:US16888677
申请日:2020-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeon Gyu You , In Gyum Kim , Gi Young Yang , Ji Su Yu , Jin Young Lim , Hak Chul Jung
IPC: H01L27/118 , H01L27/02
Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.
-
-
-
-
-
-
-
-