公开(公告)号：US11916120B2

公开(公告)日：2024-02-27

申请号：US17740829

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Hyeon Gyu You ,  Seung Man Lim

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/40 ,  H01L29/78 ,  H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  H01L29/423 ,  H01L29/66 ,  H01L23/528 ,  G06F119/06

CPC classification number: H01L29/41791 ,  G06F30/392 ,  G06F30/3953 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/785 ,  G06F2119/06

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

公开(公告)号：US11355604B2

公开(公告)日：2022-06-07

申请号：US16857288

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Hyeon Gyu You ,  Seung Man Lim

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/40 ,  H01L29/78 ,  H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  H01L29/423 ,  H01L29/66 ,  H01L23/528 ,  G06F119/06

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

公开(公告)号：US12199040B2

公开(公告)日：2025-01-14

申请号：US17180491

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongyu You ,  Jisu Yu ,  Jae-Woo Seo ,  Seung Man Lim

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

公开(公告)号：US11810920B2

公开(公告)日：2023-11-07

申请号：US17027211

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Jae-Ho Park ,  Sanghoon Baek ,  Hyeon Gyu You ,  Seung Young Lee ,  Seung Man Lim

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11885

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.