公开(公告)号：US09098670B2

公开(公告)日：2015-08-04

申请号：US14258065

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Joong Song ,  Jae-Ho Park ,  Kwang-Ok Jeong

IPC: G06F17/50 ,  G03F7/00 ,  G03F1/70

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5077

Abstract: A double patterning layout design method includes defining critical paths including a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout includes anchoring the critical paths on the schematic circuit.

Abstract translation: 双重图案化布局设计方法包括定义包括原理图电路上的第一路径和第二路径的关键路径，以及限定分成具有第一颜色的第一掩模布局和具有第二颜色的第二掩模布局的双图案布局， 双重图案布局对应于原理图电路。 双重图案化布局的定义包括将关键路径锚定在原理图电路上。

公开(公告)号：US11488948B2

公开(公告)日：2022-11-01

申请号：US17109912

申请日：2020-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon Gyu You ,  Ji Su Yu ,  Jae-Ho Park

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  G06F30/392 ,  G06F30/394

Abstract: A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.

公开(公告)号：US11183497B2

公开(公告)日：2021-11-23

申请号：US16531327

申请日：2019-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Boong Lee ,  Jae-Ho Park ,  Sang-Hoon Baek ,  Ji-Su Yu ,  Seung-Young Lee ,  Jong-Hoon Jung

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02

Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

公开(公告)号：US09129580B2

公开(公告)日：2015-09-08

申请号：US14316179

申请日：2014-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ho Park ,  Won-Sik Kang

IPC: G09G5/00 ,  G09G3/36 ,  H02M3/07 ,  G02F1/133 ,  H02M1/00

CPC classification number: G09G3/3696 ,  G02F1/13306 ,  G09G3/3648 ,  G09G2330/02 ,  G09G2330/04 ,  H02M3/07 ,  H02M2001/009

Abstract: A voltage generator includes a boosting circuit boosting a power voltage to generate first through fourth voltages, and a boosting controller controlling the boosting circuit. The boosting controller sets the third and fourth voltages to a voltage level lower than that of a ground voltage while the first and second voltages are generated, so that a plurality of voltages may be stably generated, i.e., without latch-up.

Abstract translation: 电压发生器包括升压电路，以提高电源电压以产生第一到第四电压，以及升压控制器控制升压电路。 在产生第一和第二电压的同时，升压控制器将第三和第四电压设置为低于接地电压的电压电平，使得可以稳定地产生多个电压，即不锁定。

公开(公告)号：US20210305232A1

公开(公告)日：2021-09-30

申请号：US17109912

申请日：2020-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon Gyu You ,  Ji Su Yu ,  Jae-Ho Park

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  G06F30/392 ,  G06F30/394

Abstract: A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.

公开(公告)号：US11810920B2

公开(公告)日：2023-11-07

申请号：US17027211

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Jae-Ho Park ,  Sanghoon Baek ,  Hyeon Gyu You ,  Seung Young Lee ,  Seung Man Lim

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11885

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

公开(公告)号：US11695002B2

公开(公告)日：2023-07-04

申请号：US17720153

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US11329039B2

公开(公告)日：2022-05-10

申请号：US16842053

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/118

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US10096520B2

公开(公告)日：2018-10-09

申请号：US15392725

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

IPC: H01L21/82 ,  H01L21/02 ,  H01L21/30 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/762 ,  H01L27/02 ,  H01L27/108 ,  H01L27/11 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

公开(公告)号：US09536946B2

公开(公告)日：2017-01-03

申请号：US14833983

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ho Park ,  Taejoong Song ,  Sanghoon Baek ,  Jintae Kim ,  Giyoung Yang ,  Hyosig Won

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0642 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract translation: 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。