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    Semiconductor memory devices including a discharge circuit
    1.
    发明授权
    Semiconductor memory devices including a discharge circuit 有权
    包括放电电路的半导体存储器件

    公开(公告)号：US09087566B2

    公开(公告)日：2015-07-21

    申请号：US14038932

    申请日：2013-09-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Gi Young Yang ,  Jong Hoon Jung

    IPC: G06F12/00 ,  G11C7/12 ,  G11C11/419

    CPC classification number: G11C7/12 ,  G06F12/00 ,  G11C11/419

    Abstract: Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.

    Abstract translation: 提供半导体存储器件。 每个半导体存储器件可以包括第一和第二存储单元。 第一存储单元可以连接到位线和互补位线。 此外，每个半导体存储器件可以包括通过位线和互补位线连接到第一存储单元的放电电路。 放电电路可以被配置为在第二存储单元的读取或写入操作期间对第一存储单元进行放电。

    SEMICONDUCTOR MEMORY DEVICES INCLUDING A DISCHARGE CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES INCLUDING A DISCHARGE CIRCUIT 有权
    包括放电电路的半导体存储器件

    公开(公告)号：US20140101395A1

    公开(公告)日：2014-04-10

    申请号：US14038932

    申请日：2013-09-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Joong Song ,  Gyu Hong Kim ,  Jae Ho Park ,  Gi Young Yang ,  Jong Hoon Jung

    IPC: G11C7/12 ,  G06F12/00

    CPC classification number: G11C7/12 ,  G06F12/00 ,  G11C11/419

    Abstract: Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.

    Abstract translation: 提供半导体存储器件。 每个半导体存储器件可以包括第一和第二存储单元。 第一存储单元可以连接到位线和互补位线。 此外，每个半导体存储器件可以包括通过位线和互补位线连接到第一存储单元的放电电路。 放电电路可以被配置为在第二存储单元的读取或写入操作期间对第一存储单元进行放电。

    Integrated circuit including integrated standard cell structure
    6.
    发明授权
    Integrated circuit including integrated standard cell structure 有权

    公开(公告)号：US11244961B2

    公开(公告)日：2022-02-08

    申请号：US16888677

    申请日：2020-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon Gyu You ,  In Gyum Kim ,  Gi Young Yang ,  Ji Su Yu ,  Jin Young Lim ,  Hak Chul Jung

    IPC: H01L27/118 ,  H01L27/02

    Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

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