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    Semiconductor device having DC structure
    11.
    发明授权
    Semiconductor device having DC structure 有权
    具有直流结构的半导体器件

    公开(公告)号：US08878293B2

    公开(公告)日：2014-11-04

    申请号：US13767992

    申请日：2013-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Won-Chul Lee ,  Jin-Won Jeong

    IPC: H01L29/66 ,  H01L23/538 ,  H01L27/088

    CPC classification number: H01L23/5384 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/10879 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes an interlayer insulating layer on a substrate, and a direct contact (DC) structure vertically penetrating the interlayer insulating layer and contacting the substrate, the DC structure including a DC hole exposing the substrate, an insulating DC spacer on an inner wall of the DC hole, and a conductive DC plug on the DC spacer and filling the DC hole, the DC plug including a lower DC plug and an upper DC plug on the lower DC plug, the lower DC plug having a smaller horizontal width than that of the upper DC plug.

    Abstract translation: 半导体器件包括在基板上的层间绝缘层和垂直穿过层间绝缘层并与基板接触的直接接触（DC）结构，包括露出基板的DC孔的DC结构，内壁上的绝缘DC间隔物 DC直流插头和直流隔离件上的导电直流插头，并填充直流孔，直流插头包括下直流插头的下部直流插头和上部直流插头，下部直流插头的水平宽度小于 的上部直流插头。

    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230045674A1

    公开(公告)日：2023-02-09

    申请号：US17662306

    申请日：2022-05-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang

    IPC: H01L27/108

    Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

    Semiconductor devices with peripheral gate structures
    13.
    发明授权
    Semiconductor devices with peripheral gate structures 有权

    公开(公告)号：US11502082B2

    公开(公告)日：2022-11-15

    申请号：US16902338

    申请日：2020-06-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

    Semiconductor devices with peripheral gate structures
    14.
    发明授权
    Semiconductor devices with peripheral gate structures 有权

    公开(公告)号：US10714478B2

    公开(公告)日：2020-07-14

    申请号：US16532857

    申请日：2019-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

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