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    MATRIX MULTIPLIER AND OPERATION METHOD OF MATRIX MULTIPLY DEVICE INCLUDING THE SAME
    12.
    发明申请
    MATRIX MULTIPLIER AND OPERATION METHOD OF MATRIX MULTIPLY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250139193A1

    公开(公告)日：2025-05-01

    申请号：US18820372

    申请日：2024-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Younho JEON ,  Jae Hun JANG ,  Suchang KIM ,  Yeo-Reum PARK ,  Hong Rak SON ,  Jihoon LIM ,  Se Jung KWON ,  Byeoung Wook KIM ,  Baeseong PARK ,  Dongsoo LEE

    IPC: G06F17/16

    Abstract: A matrix multiplier includes an input vector scaler generating a first quantization scaled input vector based on a first input vector, a plurality of common scale coefficients, and first-to-Rth multiplication scale coefficients, a first data type converter generating a first fixed point quantization scaled input vector based on the first quantization scaled input vector, an element array comprising a first processing element generating a first fixed point output element based on the first fixed point quantization scaled input vector and first plurality of quantization sign bits, and a second processing element generating a second fixed point output element based on the first fixed point quantization scaled input vector and second plurality of quantization sign bits, and a second data type converter generating and outputting first and second output elements by converting data types of the first and second fixed point output elements.

    OPERATING METHOD OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM
    15.
    发明申请
    OPERATING METHOD OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM 有权
    非易失性存储器件和非易失性存储器系统的操作方法

    公开(公告)号：US20150220283A1

    公开(公告)日：2015-08-06

    申请号：US14616153

    申请日：2015-02-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun Chu OH ,  JongHa KIM ,  Junjin KONG ,  Hong Rak SON

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246

    Abstract: An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation.

    Abstract translation: 一种非易失性存储器件的操作方法，包括从外部设备接收多个子页面数据和写入命令; 执行预主程序操作，使得所述多个子页数据中的至少一个存储在所述主区域中包括的所述第二多个存储单元中; 执行缓冲的程序操作，使得其他接收的子页数据存储在包括在缓冲区中的第一多个存储单元中; 以及执行重主程序操作，使得经受缓冲区域缓冲的程序操作的接收到的子页数据被存储在经受主程序编程操作的第二多个存储单元中。

    METHOD OF OPERATING DATA COMPRESSION CIRCUIT AND DEVICES TO PERFORM THE SAME
    16.
    发明申请
    METHOD OF OPERATING DATA COMPRESSION CIRCUIT AND DEVICES TO PERFORM THE SAME 有权
    操作数据压缩电路的方法和执行相同的设备

    公开(公告)号：US20140195702A1

    公开(公告)日：2014-07-10

    申请号：US14146846

    申请日：2014-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Man Keun SEO ,  Dae Wook KIM ,  Hong Rak SON ,  Jun Jin KONG

    IPC: G06F5/14

    CPC classification number: H03M7/30 ,  G06F13/14 ,  G06F13/1668 ,  H03M7/3084 ,  H03M7/3091

    Abstract: A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.

    Abstract translation: 一种操作数据压缩电路的方法包括接收和存储多个数据块，直到高速缓存满了，并且当高速缓存已满时将已经存储在高速缓存中的数据块写入缓冲存储器。 该方法还包括对每个数据块执行强制文字/文字编码，而不管每个数据块在高速缓存满时的重复性。

    ERROR CORRECTING CODE ENCODING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    17.
    发明公开
    ERROR CORRECTING CODE ENCODING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240340025A1

    公开(公告)日：2024-10-10

    申请号：US18520707

    申请日：2023-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kijun JEON ,  Kyoungbin PARK ,  Hong Rak SON ,  Dae-Yeol YANG ,  Geunyeong YU ,  Bohwan JUN ,  Youngjun HWANG

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1168 ,  H03M13/616

    Abstract: A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.

    OPERATION METHOD OF MEMORY CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE
    18.
    发明申请
    OPERATION METHOD OF MEMORY CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE 有权

    公开(公告)号：US20230092380A1

    公开(公告)日：2023-03-23

    申请号：US17885823

    申请日：2022-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonghyeog CHOI ,  Dong-Min SHIN ,  Hong Rak SON ,  Hyeonjong SONG ,  Yeongcheol JO

    IPC: G06F3/06

    Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.

    POLAR CODE DECODING APPARATUS AND METHOD
    20.
    发明申请
    POLAR CODE DECODING APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20190140665A1

    公开(公告)日：2019-05-09

    申请号：US16013053

    申请日：2018-06-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Min SHIN ,  Min Uk KIM ,  Ki Jun LEE ,  Jun Jin KONG ,  Hong Rak SON

    IPC: H03M13/29 ,  H03M13/13

    Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

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