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公开(公告)号：US20210050866A1
公开(公告)日：2021-02-18
申请号：US16823913
申请日：2020-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Min SHIN , Min Uk KIM , Young Suk RA , Tae Hyun SONG , Seong Hyeog CHOI , Hong Rak SON
Abstract: An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.
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公开(公告)号：US20250103288A1
公开(公告)日：2025-03-27
申请号：US18818742
申请日：2024-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hun JANG , Hong Rak SON , Dong-Min SHIN , JongYoon YOON , Younho JEON , Sejung KWON , Byeoungwook KIM , Baeseong PARK , Mankeun SEO , Byungmin AHN , Dongsoo LEE
Abstract: Disclosed is an accelerator performing an accumulation operation on a plurality of data, each being a floating point type. A method of operating the accelerator includes loading first data, finding a first exponent, which is a maximum value among exponents of the first data, generating aligned first fractions by performing a bit shift on first fractions of the first data based on the first exponent, and generating a first accumulated value by an accumulation operation on the aligned first fractions, loading second data, finding a second exponent, which is a maximum value among exponents of the second data, and generating a first aligned accumulated value by a bit shift on the first accumulated value, generating aligned second fractions by a bit shift on second fractions of the second data, and generating a second accumulated value by an accumulation operation on the aligned second fractions and the first aligned accumulated value.
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公开(公告)号：US20220083259A1
公开(公告)日：2022-03-17
申请号：US17237136
申请日：2021-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wi Jik LEE , Dong-Min SHIN , Young Jun HWANG , Hong Rak SON
IPC: G06F3/06
Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.
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公开(公告)号：US20250117440A1
公开(公告)日：2025-04-10
申请号：US18817733
申请日：2024-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hun JANG , Hong Rak SON , Dong-Min SHIN , JongYoon YOON , Jihoon LIM , Younho JEON , Dongsoo LEE , Sejung KWON , Byeoungwook KIM , Baeseong PARK
Abstract: At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.
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公开(公告)号：US20210281280A1
公开(公告)日：2021-09-09
申请号：US17314768
申请日：2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun JANG , Dong-Min SHIN , Heon Hwa CHEONG , Jun Jin KONG , Hong Rak SON , Se Jin LIM
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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Patent Agency Ranking
公开(公告)号：US20250117257A1
公开(公告)日：2025-04-10
申请号：US18830998
申请日：2024-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungmin AHN , Hong Rak SON , Dong-Min SHIN , Dae-Yeol YANG , JongYoon YOON , Jae Hun JANG , Se Jung KWON , Byeongwook KIM , Baeseong PARK , Dongsoo LEE
Abstract: Disclosed is an accelerator device which includes an interface circuit that communicates with an external device, a memory that stores first data received through the interface circuit, a polar encoder that performs polar encoding with respect to the first data provided from the memory and to output a result of the polar encoding as second data, and an accelerator core that loads the second data. The first data are compressed weight data, the second data are decompressed weight data, the accelerator core is configured to perform machine learning-based inference based on the second data, and the first data are variable in length.
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公开(公告)号：US20230266916A1
公开(公告)日：2023-08-24
申请号：US18310978
申请日：2023-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wi Jik LEE , Dong-Min SHIN , Young Jun HWANG , Hong Rak SON
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.
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8.发明申请公开(公告)号：US20150263767A1
公开(公告)日：2015-09-17
申请号：US14645073
申请日：2015-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dong-Min SHIN , Jun-jin KONG , Ki-Jun LEE , Myung-Kyu LEE , Kyeong-Cheol YANG , Seung-Chan LIM
IPC: H03M13/45
CPC classification number: H03M13/13 , H03M13/134
Abstract: A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.
Abstract translation: 用于极性码的列表解码方法包括：生成用于输入码字符号的树型解码图; 生成树型解码图，包括：基于解码路径的可靠性生成解码边缘被添加到的解码路径列表，生成解码路径列表，使得在基于解码边缘生成的解码路径中， 在所述解码路径列表内以高似然概率的顺序在阈值数量的关键路径内解码路径，并且从所述解码路径列表的解码路径中确定对应于具有最大似然概率的解码路径的估计值， 作为信息词。
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公开(公告)号：US20230092380A1
公开(公告)日：2023-03-23
申请号：US17885823
申请日：2022-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seonghyeog CHOI , Dong-Min SHIN , Hong Rak SON , Hyeonjong SONG , Yeongcheol JO
IPC: G06F3/06
Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.
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公开(公告)号：US20190140665A1
公开(公告)日：2019-05-09
申请号：US16013053
申请日：2018-06-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Min SHIN , Min Uk KIM , Ki Jun LEE , Jun Jin KONG , Hong Rak SON
Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.
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