公开(公告)号：US20240202067A1

公开(公告)日：2024-06-20

申请号：US18223124

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghyeog CHOI ,  Changkyu Seol ,  Dong Kim ,  Inhoon Park ,  Jinsoo Lim ,  Youngdon Choi ,  Junghwan Choi

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A method of operating a storage device includes: periodically performing a patrol read operation on a memory device; storing failure information according to the patrol read operation in a buffer memory; generating an uncorrectable error as a result of a first error correction operation performed on read data of the memory device; loading the failure information from the buffer memory; and performing a second error correction operation on the read data by using the failure information.

公开(公告)号：US20230092380A1

公开(公告)日：2023-03-23

申请号：US17885823

申请日：2022-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghyeog CHOI ,  Dong-Min SHIN ,  Hong Rak SON ,  Hyeonjong SONG ,  Yeongcheol JO

IPC: G06F3/06

Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.

公开(公告)号：US20230057932A1

公开(公告)日：2023-02-23

申请号：US17685024

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanwoo NOH ,  Hyeonjong SONG ,  Wijik LEE ,  Hongrak SON ,  Dongmin SHIN ,  Seonghyeog CHOI

IPC: G06F3/06

Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

公开(公告)号：US20220199185A1

公开(公告)日：2022-06-23

申请号：US17392781

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoon YOON ,  Hyeonjong SONG ,  Seonghyeog CHOI ,  Hongrak SON

IPC: G11C29/42 ,  G11C29/18 ,  G11C16/34

Abstract: In a method of predicting a remaining lifetime of the nonvolatile memory device, a read sequence is performed. The read sequence includes a plurality of read operations, and at least one of the plurality of read operations is sequentially performed until read data stored in the nonvolatile memory device is successfully retrieved. Sequence class and error correction code (ECC) decoding information are generated. A life stage of the nonvolatile memory device is determined based on at least one of the sequence class and the ECC decoding information. When it is determined that the nonvolatile memory device corresponds to a first life stage, a coarse prediction on the remaining lifetime of the nonvolatile memory device is performed. When it is determined that the nonvolatile memory device corresponds to a second life stage after the first life stage, a fine prediction on the remaining lifetime of the nonvolatile memory device is performed.