公开(公告)号：US20250117440A1

公开(公告)日：2025-04-10

申请号：US18817733

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hun JANG ,  Hong Rak SON ,  Dong-Min SHIN ,  JongYoon YOON ,  Jihoon LIM ,  Younho JEON ,  Dongsoo LEE ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK

IPC: G06F17/16 ,  G06F5/01

Abstract: At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.

公开(公告)号：US20230185452A1

公开(公告)日：2023-06-15

申请号：US17865621

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsuk RA ,  Hanbyeul NA ,  Kwanwoo NOH ,  Mankeun SEO ,  Hong Rak SON ,  Jae Hun JANG

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

公开(公告)号：US20210281280A1

公开(公告)日：2021-09-09

申请号：US17314768

申请日：2021-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hun JANG ,  Dong-Min SHIN ,  Heon Hwa CHEONG ,  Jun Jin KONG ,  Hong Rak SON ,  Se Jin LIM

IPC: H03M13/37 ,  H03M13/03 ,  G06F13/16 ,  G06F11/08 ,  G06F11/10

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

公开(公告)号：US20250103288A1

公开(公告)日：2025-03-27

申请号：US18818742

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hun JANG ,  Hong Rak SON ,  Dong-Min SHIN ,  JongYoon YOON ,  Younho JEON ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK ,  Mankeun SEO ,  Byungmin AHN ,  Dongsoo LEE

IPC: G06F7/485 ,  G06F5/01 ,  G06F7/22

Abstract: Disclosed is an accelerator performing an accumulation operation on a plurality of data, each being a floating point type. A method of operating the accelerator includes loading first data, finding a first exponent, which is a maximum value among exponents of the first data, generating aligned first fractions by performing a bit shift on first fractions of the first data based on the first exponent, and generating a first accumulated value by an accumulation operation on the aligned first fractions, loading second data, finding a second exponent, which is a maximum value among exponents of the second data, and generating a first aligned accumulated value by a bit shift on the first accumulated value, generating aligned second fractions by a bit shift on second fractions of the second data, and generating a second accumulated value by an accumulation operation on the aligned second fractions and the first aligned accumulated value.

公开(公告)号：US20220083259A1

公开(公告)日：2022-03-17

申请号：US17237136

申请日：2021-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wi Jik LEE ,  Dong-Min SHIN ,  Young Jun HWANG ,  Hong Rak SON

IPC: G06F3/06

Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.

公开(公告)号：US20250139194A1

公开(公告)日：2025-05-01

申请号：US18823847

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd. ,  NAVER CORPORATION

Inventor： Younho JEON ,  Hong Rak SON ,  Wonsuk SONG ,  Younggeon YOO ,  JongYoon YOON ,  Jihoon LIM ,  Jae Hun JANG ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK ,  Dongsoo LEE

IPC: G06F17/16 ,  G06F5/01 ,  H03M7/24

Abstract: A matrix multiplier includes an input vector scaler configured to generate a first scaled input vector based on a first input vector and a plurality of quantization scale coefficients, a first data type converter configured to generate a first fixed-point scaled input vector based on the first scaled input vector, a processing element array including a first processing element configured to generate a first fixed-point output element based on the first fixed-point scaled input vector and first plurality of quantization sign values and a second processing element configured to generate a second fixed-point output element based on the first fixed-point scaled input vector and second plurality of quantization sign values, and a second data type converter configured to generate first and second output elements by converting data type of the first and second fixed-point output elements, and to output a first output vector including the first and second output elements.

公开(公告)号：US20240289267A1

公开(公告)日：2024-08-29

申请号：US18384646

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyeon KIM ,  Hong Rak SON ,  Jae Hun JANG ,  Mankeun SEO ,  Yong Ho SONG

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.

公开(公告)号：US20210149762A1

公开(公告)日：2021-05-20

申请号：US16914890

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangseok LEE ,  Dong-min SHIN ,  Geunyeoung YU ,  Bohwan JUN ,  Hee Youl KWAK ,  Hong Rak SON

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/35

Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

公开(公告)号：US20210050866A1

公开(公告)日：2021-02-18

申请号：US16823913

申请日：2020-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Min SHIN ,  Min Uk KIM ,  Young Suk RA ,  Tae Hyun SONG ,  Seong Hyeog CHOI ,  Hong Rak SON

IPC: H03M13/15 ,  H03M13/29 ,  H03M13/11

Abstract: An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

公开(公告)号：US20200211656A1

公开(公告)日：2020-07-02

申请号：US16817043

申请日：2020-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH ,  Pilsang YOON ,  Jun Jin KONG ,  Jisu KIM ,  Hong Rak SON ,  Jinbae BANG ,  Daeseok BYEON ,  Taehyun SONG ,  Dongjin SHIN ,  Dongsup JIN

IPC: G11C16/28 ,  G11C29/02 ,  G11C16/04 ,  G11C29/50 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.