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    MATRIX MULTIPLIER AND OPERATION METHOD OF MATRIX MULTIPLY DEVICE INCLUDING THE SAME
    1.
    发明申请
    MATRIX MULTIPLIER AND OPERATION METHOD OF MATRIX MULTIPLY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250139193A1

    公开(公告)日：2025-05-01

    申请号：US18820372

    申请日：2024-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Younho JEON ,  Jae Hun JANG ,  Suchang KIM ,  Yeo-Reum PARK ,  Hong Rak SON ,  Jihoon LIM ,  Se Jung KWON ,  Byeoung Wook KIM ,  Baeseong PARK ,  Dongsoo LEE

    IPC: G06F17/16

    Abstract: A matrix multiplier includes an input vector scaler generating a first quantization scaled input vector based on a first input vector, a plurality of common scale coefficients, and first-to-Rth multiplication scale coefficients, a first data type converter generating a first fixed point quantization scaled input vector based on the first quantization scaled input vector, an element array comprising a first processing element generating a first fixed point output element based on the first fixed point quantization scaled input vector and first plurality of quantization sign bits, and a second processing element generating a second fixed point output element based on the first fixed point quantization scaled input vector and second plurality of quantization sign bits, and a second data type converter generating and outputting first and second output elements by converting data types of the first and second fixed point output elements.

    MEMORY CONTROLLER PERFORMING SELECTIVE AND PARALLEL ERROR CORRECTION, SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY DEVICE
    6.
    发明申请
    MEMORY CONTROLLER PERFORMING SELECTIVE AND PARALLEL ERROR CORRECTION, SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20220156146A1

    公开(公告)日：2022-05-19

    申请号：US17510898

    申请日：2021-10-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyeokjun CHOE ,  Heehyun NAM ,  Jeongho LEE ,  Younho JEON

    IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

    Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

    INTERFACE CIRCUIT FOR PROVIDING EXTENSION PACKET AND PROCESSOR INCLUDING THE SAME
    8.
    发明申请
    INTERFACE CIRCUIT FOR PROVIDING EXTENSION PACKET AND PROCESSOR INCLUDING THE SAME 有权

    公开(公告)号：US20220141322A1

    公开(公告)日：2022-05-05

    申请号：US17466742

    申请日：2021-09-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Younho JEON ,  Hyeokjun CHOE ,  Jeongho LEE

    IPC: H04L29/06

    Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

    SYSTEM, DEVICE AND METHOD FOR INDIRECT ADDRESSING
    9.
    发明申请
    SYSTEM, DEVICE AND METHOD FOR INDIRECT ADDRESSING 有权

    公开(公告)号：US20220114118A1

    公开(公告)日：2022-04-14

    申请号：US17378354

    申请日：2021-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeongho LEE ,  Ipoom JEONG ,  Younggeon YOO ,  Younho JEON

    IPC: G06F13/16 ,  G06F3/06

    Abstract: A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.

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