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    STORAGE DEVICE AND METHOD OF OPERATING THE SAME
    1.
    发明申请
    STORAGE DEVICE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220083847A1

    公开(公告)日：2022-03-17

    申请号：US17230331

    申请日：2021-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungroh YOON ,  Hyeokjun CHOE ,  Seongsik PARK ,  Seijoon KIM

    IPC: G06N3/063 ,  G06F12/10 ,  G06F9/50

    Abstract: A method of operating a storage device including a neural network processor includes outputting, by a controller device, a trigger signal instructing the neural network processor to perform a neural network operation in response to a command from a host device, requesting, by a neural network processor, target model data about parameters of a target model and instruction data for instructing the neural network operation to a memory device storing the target model data and the instruction data in response to the trigger signal, receiving, by the neural network processor, the target model data and the instruction data from the memory device and outputting, by the neural network processor, inference data based on the target model data and the instruction data.

    MEMORY CONTROLLER PERFORMING SELECTIVE AND PARALLEL ERROR CORRECTION, SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY DEVICE
    3.
    发明申请
    MEMORY CONTROLLER PERFORMING SELECTIVE AND PARALLEL ERROR CORRECTION, SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20220156146A1

    公开(公告)日：2022-05-19

    申请号：US17510898

    申请日：2021-10-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyeokjun CHOE ,  Heehyun NAM ,  Jeongho LEE ,  Younho JEON

    IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

    Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

    STORAGE DEVICE AND METHOD OF OPERATING THE SAME
    6.
    发明公开
    STORAGE DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20230259750A1

    公开(公告)日：2023-08-17

    申请号：US18310008

    申请日：2023-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungroh YOON ,  Hyeokjun CHOE ,  Seongsik PARK ,  Seijoon KIM

    IPC: G06N3/063 ,  G06F9/50 ,  G06F12/10

    CPC classification number: G06N3/063 ,  G06F9/5061 ,  G06F9/5016 ,  G06F12/10

    Abstract: A method of operating a storage device including a neural network processor includes outputting, by a controller device, a trigger signal instructing the neural network processor to perform a neural network operation in response to a command from a host device, requesting, by a neural network processor, target model data about parameters of a target model and instruction data for instructing the neural network operation to a memory device storing the target model data and the instruction data in response to the trigger signal, receiving, by the neural network processor, the target model data and the instruction data from the memory device and outputting, by the neural network processor, inference data based on the target model data and the instruction data.

    INTERFACE CIRCUIT FOR PROVIDING EXTENSION PACKET AND PROCESSOR INCLUDING THE SAME
    7.
    发明申请
    INTERFACE CIRCUIT FOR PROVIDING EXTENSION PACKET AND PROCESSOR INCLUDING THE SAME 有权

    公开(公告)号：US20220141322A1

    公开(公告)日：2022-05-05

    申请号：US17466742

    申请日：2021-09-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Younho JEON ,  Hyeokjun CHOE ,  Jeongho LEE

    IPC: H04L29/06

    Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

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