公开(公告)号：US20240103755A1

公开(公告)日：2024-03-28

申请号：US18531094

申请日：2023-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb JEONG ,  Hongju KAL ,  Won Woo RO ,  Seokmin LEE ,  Gun KO

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

公开(公告)号：US20220164286A1

公开(公告)日：2022-05-26

申请号：US17408767

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb JEONG ,  Heehyun NAM ,  Jeongho LEE

IPC: G06F12/0806 ,  G06F12/0862 ,  G06F12/02

Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.

公开(公告)号：US20250138731A1

公开(公告)日：2025-05-01

申请号：US18762697

申请日：2024-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsub SONG ,  Hyeonho SONG ,  Donghun LEE ,  Wonseb JEONG

IPC: G06F3/06

Abstract: Disclosed is an operation method of a storage device which is connected to a compute express link (CXL) switch. The method includes receiving a first access request from a first host through the CXL switch, performing an operation corresponding to the first access request, detecting a change in first metadata managed by the first host, based on the first access request, and transmitting first update information corresponding to the change in the first metadata to a second host sharing the storage device through the CXL switch.

公开(公告)号：US20220147476A1

公开(公告)日：2022-05-12

申请号：US17368981

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heehyun NAM ,  Jeongho LEE ,  Wonseb JEONG ,  Ipoom JEONG ,  Hyeokjun CHOE

IPC: G06F13/28 ,  G06F3/06

Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.

公开(公告)号：US20230384960A1

公开(公告)日：2023-11-30

申请号：US18141007

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb JEONG ,  SOO-YOUNG Ji

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0659 ,  G06F3/0688 ,  G06F3/0619

Abstract: Disclosed are a storage system and an operation method therefor. The storage system includes: a host system; and a plurality of storage sets configured to interface with the host system. At least one of the plurality of storage sets includes: a first memory region; a second memory region; and a third memory region, and the at least one of the plurality of storage sets is configured to move data stored in the third memory region to a selected memory region among the first memory region and the second memory region based on a data access feature.

公开(公告)号：US20220398032A1

公开(公告)日：2022-12-15

申请号：US17837286

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb JEONG ,  Hongju KAL ,  Won Woo RO ,  Seokmin LEE ,  Gun KO

IPC: G06F3/06

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.