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公开(公告)号:US20250048352A1
公开(公告)日:2025-02-06
申请号:US18920417
申请日:2024-10-18
Inventor: Ilsong SIM , Gun KO , Won Woo RO , Sangeon KIM , Seunghyun MIN
IPC: H04W72/1263 , H04W72/543
Abstract: A network scheduling device and method are disclosed. The scheduling method comprises: determining whether a set condition for a transmission time interval (TTI) is satisfied, and, if the set condition is satisfied, storing in a memory, at each TTI until the set TTI elapses, a data array comprising the network state of the current TTI, the scheduler type selected at the network state of the current TTI, the network state of the next TTI, and the actual compensation value for the network state of the current TTI, and updating the parameters of the first neural network based on at least one of the data arrays stored in the memory, and, if the set condition is not satisfied, inputting the network state of the current TTI to the first neural network and selecting a scheduler using the output of the first neural network based on the input network state of the current TTI.
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公开(公告)号:US20220398032A1
公开(公告)日:2022-12-15
申请号:US17837286
申请日:2022-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseb JEONG , Hongju KAL , Won Woo RO , Seokmin LEE , Gun KO
IPC: G06F3/06
Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.
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公开(公告)号:US20240103755A1
公开(公告)日:2024-03-28
申请号:US18531094
申请日:2023-12-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseb JEONG , Hongju KAL , Won Woo RO , Seokmin LEE , Gun KO
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.
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